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TEA1750T/N1/DG,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
TEA1750_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 15 December 2008 10 of 29
NXP Semiconductors
TEA1750
GreenChip III SMPS control IC
7.2.6 Burst mode control
When the output power of the flyback converter (see Section 7.3) is low, the flyback
converter switches over to frequency reduction mode. When frequency reduction mode is
entered by the flyback controller, the power factor correction circuit switches to burst mode
control.
In burst mode control, switching of the power factor correction circuit is inhibited until the
voltage on the VOSENSE pin has dropped to V
burst(L)
. Switching then restarts with a
soft-start to avoid audible noise (see Section 7.2.5). As soon as the voltage on the
VOSENSE pin reaches V
burst(H)
the soft-stop circuit is activated, again to avoid audible
noise. During the soft-stop time the output voltage of the power factor correction circuit
overshoots, depending on the soft-start resistor and capacitor, R
SS1
and C
SS1,
on the
PFCSENSE pin. As the V
burst(H)
voltage is well below the V
reg(VOSENSE)
voltage, the PFC
output voltage does not reach the normal operation output voltage of the power factor
correction circuit in a typical application due to this overshoot.
The burst mode repetition rate is defined by the output power and the value of the bus
capacitor, C
bus
.
During burst mode operation the PFCCOMP pin is clamped between a voltage of
2.7 V (typ) and 3.9 V (typ). The lower clamp voltage limits the maximum power that is
delivered during burst mode operation and yields a more sinusoidal input current during
the burst pulse. The upper clamp voltage ensures that the PFC can return to its normal
regulation point in a limited amount of time when returning from burst mode.
As soon as the flyback converter leaves frequency reduction mode, the power factor
correction circuit restores normal operation. To prevent continuous on and off switching of
the PFC circuit, a small hysteresis is built in (50 mV (typ) on the FBCTRL pin).
Fig 5. Soft start-up and soft stop of PFC
SOFT START
SOFT STOP
CONTROL
OCP
+
11
PFCSENSE
0.5 V
I
start(soft)PFC ≤ 60 µA
S1
R
SS1
C
SS1
R
SENSE1
014aaa018
TEA1750_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 15 December 2008 11 of 29
NXP Semiconductors
TEA1750
GreenChip III SMPS control IC
7.2.7 Overcurrent protection (PFCSENSE pin)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor (R
SENSE1
) on the source of the external MOSFET. The voltage is
measured via the PFCSENSE pin.
7.2.8 Mains undervoltage lock-out / brownout protection (VINSENSE pin)
To prevent the PFC from operating at very low mains input voltages, the voltage on the
VINSENSE pin is sensed continuously. As soon as the voltage on this pin drops below the
V
stop(VINSENSE)
level, switching of the PFC is stopped. If the low mains situation continues,
the PFC bus voltage eventually drops. The voltage on the VOSENSE pin then drops below
the V
start(fb)
level and the flyback converter is also disabled.
The voltage on pin VINSENSE is clamped to a minimum value,
(V
start(VINSENSE)
−∆V
pu(VINSENSE)
) for a fast restart as soon as the mains input voltage is
restored after a mains dropout.
7.2.9 Overvoltage protection (VOSENSE pin)
To prevent output overvoltage during load steps and mains transients, an overvoltage
protection circuit is built in.
As soon as the voltage on the VOSENSE pin exceeds the V
ovp(VOSENSE)
level, switching of
the power factor correction circuit is inhibited. Switching of the PFC recommences as
soon as the VOSENSE pin voltage drops below the V
ovp(VOSENSE)
level again.
When the resistor between pin VOSENSE and ground is open, the overvoltage protection
is also triggered.
7.2.10 PFC open loop protection (VOSENSE pin)
The power factor correction circuit does not start switching until the voltage on the
VOSENSE pin is above the V
th(ol)(VOSENSE)
level. This protects the circuit from open loop
and VOSENSE short situations. As the VOSENSE pin draws a small input current,
switching is also inhibited when the pin is left open.
Fig 6. Burst mode control
V
burst(H)
V
burst(L)
soft-stopton controlsoft-start
V
VOSENSE
envelop of
peak current
014aaa019
TEA1750_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 15 December 2008 12 of 29
NXP Semiconductors
TEA1750
GreenChip III SMPS control IC
7.2.11 Driver (pin PFCDRIVER)
The driver circuit to the gate of the power MOSFET has a current sourcing capability of
typically 500 mA and a current sink capability of typically 1.2 A. This permits fast turn-on
and turn-off of the power MOSFET for efficient operation.
7.3 Flyback controller
The TEA1750 includes a controller for a flyback converter. The flyback converter operates
in quasi-resonant or discontinuous conduction mode with valley switching. The auxiliary
winding of the flyback transformer provides demagnetization detection and powers the IC
after start-up.
7.3.1 Multi mode operation
The TEA1750 flyback controller can operate in multi modes; see Figure 7.
At high output power the converter switches to quasi-resonant mode. The next converter
stroke is started after demagnetization of the transformer current. In quasi-resonant mode
switching losses are minimized as the converter only switches on when the voltage across
the external MOSFET is at its minimum (valley switching, see also Section 7.3.2).
To prevent high frequency operation at lower loads, the quasi-resonant operation changes
to discontinuous mode operation with valley skipping in which the switching frequency is
limited for EMI to f
sw(fb)(max)
(125 kHz typ). Again, the external MOSFET is only switched
on when the voltage across the MOSFET is at its minimum.
At very low power and standby levels the frequency is controlled down by a voltage
controlled oscillator (VCO). The minimum frequency can be reduced to zero. During
frequency reduction mode, the primary peak current is kept at a minimal level of Ipkmax/4
to maintain a high efficiency. (Ipkmax is the maximum primary peak current set by the
sense resistor and the maximum sense voltage.) As the primary peak current is low in
frequency reduction mode operation (Ipk = Ipkmax/4), no audible noise is noticeable at
switching frequencies in the audible range. Valley switching is also active in this mode.
Fig 7. Multi mode operation flyback
discontinuous
with valley
switching
quasi resonant
PFC burst mode
frequency
reduction
f
sw(fb)max
output power
switching frequency
014aaa025
PFC on
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TEA1750T/N1/DG,518

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Manufacturer:
NXP Semiconductors
Description:
AC/DC Converters 12V -80uA 125KHz
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