DATASHEET
5P49V5925 MARCH 3, 2017 1 ©2017 Integrated Device Technology, Inc.
Programmable Clock Generator 5P49V5925
Description
The 5P49V5925 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I
2
C
interface. This is IDT’s fifth generation of programmable clock
technology (VersaClock
®
5).
The frequencies are generated from a single reference clock.
The reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I
2
C
addresses to allow multiple devices to be used in a system.
Pin Assignment
Features
Generates up to four independent output frequencies
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs
Four fractional output dividers (FODs)
Independent Spread Spectrum capability on each output
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I
2
C serial programming interface
Five LVCMOS outputs, including one reference output
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 200MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable slew rate control
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core V
DDD
, V
DDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
1
7
24-pin VFQFPN
19
13
XOUT
XIN/REF
V
DDO
3
CLKIN
NC
OUT2
CLKINB
CLKSEL
OUT3
NC
V
DDO
2
V
DDA
SD/OE
SEL1/SDA
SEL0/SCL
V
DDO
4
NC
OUT4
NC
OUT1
V
DDO
1
V
DDD
V
DDO
0
OUT0_SEL_I2CB
EPAD
GND
2
3
4
5
6
8
9
10 11 12
14
15
16
17
18
2021222324
PROGRAMMABLE CLOCK GENERATOR 2 MARCH 3, 2017
5P49V5925 DATASHEET
Functional Block Diagram
Applications
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1 GbE and 10 GbE
XIN/REF
XOUT
CLKIN
CLKINB
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
V
DDA
V
DDD
V
DDO
0
OUT0_SEL_I2CB
V
DDO
1
OUT1
V
DDO
2
OUT2
V
DDO
3
OUT3
V
DDO
4
OUT4
FOD1
FOD2
FOD3
FOD4
PLL
OTP
and
Control Logic
MARCH 3, 2017 3 PROGRAMMABLE CLOCK GENERATOR
5P49V5925 DATASHEET
Table 1:Pin Descriptions
Number Name Type Description
1 CLKIN Input
Internal
Pull-down
Differential clock input. Weak 100kohms internal pull-down.
2 CLKINB Input
Internal
Pull-down
Complementary differential clock input. Weak 100kohms internal pull-down.
3 XOUT Input
Crystal Oscillator interface output.
4 XIN/REF Input
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure that
the input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF
Interface”.
5V
DDA
Power
Analog functions power supply pin. Connect to 1.8V to 3.3V. V
DDA
and V
DDD
should
have the same voltage applied.
6 CLKSEL Input
Internal
Pull-down
Input clock select. Selects the active input reference source in manual switchover
mode.
0 = XIN/REF, XOUT (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I2C programming as shown in Table 4.
7 SD/OE Input
Internal
Pull-down
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for SD/OE
pin to be configured as SD. The SP bit (0x02) controls the polarity of the signal to be
either active HIGH or LOW only when pin is configured as OE (Default is active
LOW.) Weak internal pull down resistor. When configured as SD, device is shut
down and the single-ended LVCMOS outputs are driven low. When configured as
OE, and outputs are disabled, the outputs can be selected to be tri-stated or driven
high/low, depending on the programming bits as shown in the SD/OE Pin Function
Truth table.
8 SEL1/SDA Input
Internal
Pull-down
Configuration select pin, or I
2
C SDA input as selected by OUT0_SEL_I2CB. Weak
internal pull down resistor.
9 SEL0/SCL Input
Internal
Pull-down
Configuration select pin, or I
2
C SCL input as selected by OUT0_SEL_I2CB. Weak
internal pull down resistor.
10 V
DDO
4 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT4.
11 OUT4 Output Output Clock 4. Please refer to the Output Drivers section for more details.
12 NC No connect.
13 NC No connect.
14 OUT3 Output Output Clock 3. Please refer to the Output Drivers section for more details.
15 V
DDO
3 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT3.
16 NC No connect.
17 OUT2 Output Output Clock 2. Please refer to the Output Drivers section for more details.
18 V
DDO
2 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT2.
19 NC No connect.
20 OUT1 Output Output Clock 1. Please refer to the Output Drivers section for more details.
21 V
DDO
1 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT1.
22 V
DDD
Power
Digital functions power supply pin. Connect to 1.8 to 3.3V. V
DDA
and V
DDD
should
have the same voltage applied.

5P49V5925B000NLGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products VersaClock 5 CLK Gen 3 LVCMOS 200MHz
Lifecycle:
New from this manufacturer.
Delivery:
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