PROGRAMMABLE CLOCK GENERATOR 16 MARCH 3, 2017
5P49V5925 DATASHEET
Table 17:AC Timing Electrical Characteristics
(V
DDO
= 3.3V+5% or 2.5V+5% or 1.8V ±5%, TA = -40°C to +85°C)
(Spread Spectrum Generation = OFF)
Symbol Parameter Test Conditions Min. Typ. Max. Units
f
IN
1
Input Frequency Input frequency limit (XIN)
840MHz
Input frequency limit (REF)
1200MHz
Input frequency limit (CLKIN, CLKINB)
1200MHz
f
OUT
Output Frequency Single ended clock output limit (LVCMOS)
1200MHz
f
VCO
VCO Frequency VCO operating frequency range
2600 2900 MHz
f
PFD
PFD Frequency PFD operating frequency range
1
1
150 MHz
f
BW
Loop Bandwidth Input frequency = 25MHz
0.06 0.9 MHz
t2
Input Duty Cycle Duty Cycle
45 50 55 %
t3
5
Output Duty Cycle Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX= 2.5V or 3.3V
45 50 55 %
Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX=1.8V
40 50 60 %
Measured at VDD/2, Reference output
OUT0 (5MHz - 120MHz) with 50% duty cycle input
40 50 60 %
Measured at VDD/2, Reference output
OUT0 (150.1MHz - 200MHz) with 50% duty cycle
input
30 50 70 %
t4
2
Slew Rate, SLEW[1:0] = 00 Single-ended 3.3V LVCMOS output clock rise and
fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=3.3V
1.0 2.2 V/ns
Slew Rate, SLEW[1:0] = 01
1.2 2.3 V/ns
Slew Rate, SLEW[1:0] = 10
1.3 2.4 V/ns
Slew Rate, SLEW[1:0] = 11
1.7 2.7 V/ns
Slew Rate, SLEW[1:0] = 00 Single-ended 2.5V LVCMOS output clock rise and
fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=2.5V
0.6 0.3 V/ns
Slew Rate, SLEW[1:0] = 01
0.7 1.4 V/ns
Slew Rate, SLEW[1:0] = 10
0.6 1.4 V/ns
Slew Rate, SLEW[1:0] = 11
1.0 1.7 V/ns
Slew Rate, SLEW[1:0] = 00 Single-ended 1.8V LVCMOS output clock rise and
fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=1.8V
0.3 0.7 V/ns
Slew Rate, SLEW[1:0] = 01
0.4 0.8 V/ns
Slew Rate, SLEW[1:0] = 10
0.4 0.9 V/ns
Slew Rate, SLEW[1:0] = 11
0.7 1.2 V/ns
