PROGRAMMABLE CLOCK GENERATOR 22 MARCH 3, 2017
5P49V5925 DATASHEET
3.3V Differential LVPECL Clock Input Interface
The logic levels of 3.3V LVPECL and LVDS can exceed VIH
max for the CLKIN/B pins. Therefore the LVPECL levels must
be AC coupled to the VersaClock differential input and the DC
bias restored with external voltage dividers. A single table of
bias resistor values is provided below for both for 3.3V
LVPECL and LVDS. Vbias can be VDDD, V
DDOX
or any other
available voltage at the VersaClock receiver that is most
conveniently accessible in layout.
CLKIN, CLKINB Input Driven by a 3.3V LVPECL Driver
CLKIN, CLKINB Input Driven by an LVDS Driver
Table 21: Bias Resistors for 3.3V LVPECL and LVDS Drive to CLKIN/B
+3.3V LVPECL
Driver
Zo=50ohm
Zo=50ohm
VersaClock 5 Receiver
R9 R10
50ohm
50ohm
Vbias
Rpu1 Rpu2
CLKIN
CLKINB
RTT
50ohm
C5
0.01µF
C6
0.01µF
R15
4.7kohm
R13
4.7kohm
Vbias
(V)
Rpu1/2
(kohm)
CLKIN/B Bias Voltage
(V)
3.3 22 0.58
2.5 15 0.60
1.8 10 0.58
LVDS Driver
Zo=50ohm
Zo=50ohm
VersaClock 5 Receiver
Rterm
100ohm
Vbias
Rpu1 Rpu2
CLKIN
CLKINB
C1
0.1µF
C2
0.1µF
R1
4.7kohm
R2
4.7kohm
