Technical information DVIULC6-2x6
6/15 DocID14672 Rev 2
3 Technical information
3.1 Surge protection
The DVIULC6-2M6 is particularly optimized to perform ESD surge protection based on the
rail to rail topology.
The clamping voltage V
CL
can be calculated as follows:
with: V
F
= V
T
+ R
d
.I
p
(V
F
forward drop voltage) / (V
T
forward drop threshold voltage)
and V
TRANSIL
= V
BR
+ R
d_TRANSIL
. I
P
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically:
R
d
= 0.5 Ω and V
T
= 1.1 V.
We assume that the value of the dynamic resistance of the transil diode is typically
R
d_TRANSIL
= 0.5 Ω and V
BR
= 6.1 V
For an IEC 61000-4-2 surge Level 4 (Contact Discharge: V
g
= 8 kV, R
g
= 330 Ω),
V
BUS
= +5 V, and, in first approximation, we assume that: I
p
= V
g
/ R
g
= 24 A.
We find:
Note: The calculations do not take into account phenomena due to parasitic inductances.
3.2 Surge protection application example
If we consider that the connections from the pin V
BUS
to V
CC
, from I/O to data line, and from
GND to PCB GND plane are two tracks 10 mm long and 0.5 mm wide, we can assume that
the parasitic inductances, L
VBUS
, L
I/O
, and L
GND
, of these tracks are about 6 nH. So when
an IEC 61000-4-2 surge occurs on the data line, due to the rise time of this spike (tr = 1 ns),
the voltage V
CL
has an extra value equal to L
I/O
.dI/dt + L
GND
.dI/dt.
The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns for an IEC 61000-4-2 surge level 4 (contact
discharge V
g
= 8 kV, R
g
= 330 Ω)
The over voltage due to the parasitic inductances is:
L
I/O
.dI/dt = L
GND
.dI/dt = 6 x 24 = 144 V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be:
We can reduce as much as possible these phenomena with simple layout optimization.
V
CL
+ = V
TRANSIL
+ V
F
for positive surges
V
CL
- = - V
F
for negative surges
V
CL
+ = +31.2 V
V
CL
- = -13.1 V
V
CL
+ = +31.2 + 144 +144 = 319.2 V
V
CL
- = -13.1 - 144 -144 = -301.1 V
