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LTC3035EDDB#TRPBF

P1-P3P4-P6P7-P9P10-P12
LTC3035
10
3035f
Efficiency vs Output Current Ripple Rejection
SW1
SW2
V
IN
V
OUT
SHDN/SS
FB
MODE/SYNC
V
C
R
T
R
T
60.4k
4
6
9
10
5
3
7
8
2
*
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
C
IN
, C
BIAS
, C
OUT
: TDK C1005X5R0J105K
L1: SUMIDA CDRH6D38-100
1
GND
LTC3440
IN
BIAS
CP
CM
SHDN
OUT
GND
ADJ
LTC3035
SS
S
S
S S
S
S
S
S
S S
S
3035 TA02
C1
10µF
V
IN
= 2.7V TO 4.2V
C5 1.5nF
R3
15k
L1
10µH
Li-Ion
OFF ON
C2
22µF
C
IN
1µF
S
R2
200k
R1
357k
3.4V
600mA
C
BIAS
1µF
C
OUT
1µF
0.1µF
S
294k
V
OUT
= 3.3V
I
OUT
≤ 300mA
40.2k
+
Low Noise Li-Ion to 3.3V Supply
TYPICAL APPLICATIO
U
OUTPUT CURRENT (mA)
0.1
Burst Mode IS A REGISTERED TRADEMARK OF
LINEAR TECHNOLOGY CORPORATION
0
EFFICIENCY (%)
10
30
40
50
100
70
1
10
3035 TA02b
20
80
90
60
100
1000
Burst Mode
®
OPERATION
V
IN
= 2.7V
V
IN
= 4.2V
V
IN
= 3.6V
LTC3440
OUTPUT
AC
20mV/DIV
LTC3035
OUTPUT
AC
20mV/DIV
20µs/DIVI
OUT
= 25mA
3035 TA02c
LTC3035
11
3035f
PACKAGE DESCRIPTIO
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
0.56 ± 0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
2.15 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
14
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0 – 0.05
(DDB8) DFN 0905 REV B
0.25 ± 0.05
0.50 BSC
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
0.25 ± 0.05
2.20 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.61 ±0.05
(2 SIDES)
1.15 ±0.05
0.70 ±0.05
2.55 ±0.05
PACKAGE
OUTLINE
0.50 BSC
LTC3035
12
3035f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
RELATED PARTS
LT 1105 • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LT
®
1761 100mA, Low Noise Micropower, LDO V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, V
DO
= 0.30V, I
Q
= 20µA, I
SD
< 1µA, V
OUT
= Adj,
1.5V, 1.8V, 2V, 2.5V, 2.8V, 3V, 3.3V, 5V, ThinSOT
TM
Package.
Low Noise < 20µV
RMSP-P
, Stable with 1µF Ceramic Capacitors
LT1762 150mA, Low Noise Micropower LDO V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, V
DO
= 0.30V, I
Q
= 25µA, I
SD
< 1µA, V
OUT
= Adj,
2.5V, 3V, 3.3V, 5V, MS8 Package. Low Noise < 20µV
RMSP-P
LT1763 500mA, Low Noise Micropower LDO V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, V
DO
= 0.30V, I
Q
= 30µA, I
SD
< 1µA, V
OUT
= 1.5,
1.8V, 2.5V, 3V, 3.3V, 5V, S8 Package. Low Noise < 20µV
RMSP-P
LTC1844 150mA, Very Low Dropout LDO V
IN
: 1.6V to 6.5V, V
OUT(MIN)
= 1.25V, V
DO
= 0.08V, I
Q
= 40µA, I
SD
< 1µA, V
OUT
= Adj,
1.5V, 1.8V, 2.5V, 2.8V, 3.3V, ThinSOT Package. Low Noise < 30µV
RMSP-P
, Stable with
1µF Ceramic Capacitors
LT1962 300mA, Low Noise Micropower LDO V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, V
DO
= 0.27V, I
Q
= 30µA, I
SD
< 1µA, V
OUT
= 1.5,
1.8V, 2.5V, 3V, 3.3V, 5V, MS8 Package. Low Noise < 20µV
RMSP-P
LT3020 100mA, Low Voltage, VLDO V
IN
: 0.9V to 10V, V
OUT(MIN)
= 0.20V, V
DO
= 0.15V, I
Q
= 120µA, I
SD
< 3µA, V
OUT
= Adj,
DFN, MS8 Package
LTC3025 300mA, Micropower VLDO Linear Regulator V
IN
: 0.9V to 5.5V, V
BIAS
: 2.5V to 5.5V, V
OUT(MIN)
= 0.4V, V
DO
= 0.05V, I
Q
= 54µA,
I
SD
< 1µA, V
OUT
= Adj, DFN Package. Stable with 1µF Ceramic Capacitors
LTC3026 1.5A, Low Input Voltage VLDO Linear Regulator V
IN
: 1.14V to 3.5V (Boost Enabled), 1.14V to 5.5V (External 5V Boost),
V
OUT(MIN)
= 0.4V, V
DO
= 0.15V, I
Q
= 400µA, I
SD
< 1µA, V
OUT
= Adj,
DFN, MSOP Packages. Stable with 10µF Ceramic Capacitors
ThinSOT is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO S
U
Dual LDO Output (1.8V, 1.5V) from 2.5V Supply Rail
CP CM
0.1µF
1µF1µF
1µF
IN
LTC3035
SHDN
140k
V
OUT
= 1.8V
I
OUT
< 300mA
40.2k
GND
BIAS
V
IN
2.5V
OUT
ADJ
OFF ON
0.1µF0.1µF
1µF
IN
LTC3025
SHDN
110k
V
OUT
= 1.5V
I
OUT
< 300mA
40.2k
3035 TA03
GND
BIAS
OUT
ADJ
Dual LDO Output (1.5V, 1.2V) from 1.8V Supply Rail
CP CM
0.1µF
1µF1µF
1µF
IN
LTC3035
SHDN
110k
V
OUT
= 1.5V
I
OUT
< 300mA
40.2k
GND
BIAS
V
IN
1.8V
OUT
ADJ
OFF ON
0.1µF0.1µF
1µF
IN
LTC3025
SHDN
80k
V
OUT
= 1.2V
I
OUT
< 300mA
40.2k
3035 TA04
GND
BIAS
OUT
ADJ
P1-P3P4-P6P7-P9P10-P12

LTC3035EDDB#TRPBF

Mfr. #:
Buy LTC3035EDDB#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
LDO Voltage Regulators 300mA VLDO w/ Charge Pump Bias Generator in DFN-8
Lifecycle:
New from this manufacturer.
Delivery:
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