LTC3035
9
3035f
OPERATIO
U
Calculating Junction Temperature
Example: Given an output voltage of 1.5V, an input voltage
of 1.8V to 3V, an output current range of 0mA to 100mA
and a maximum ambient temperature of 50°C, what will
the maximum junction temperature be?
The power dissipated by the device will be approximately:
I
OUT(MAX)
(V
IN(MAX)
– V
OUT
)
where:
I
OUT(MAX)
= 100mA
V
IN(MAX)
= 3V
so:
P = 100mA(3V – 1.5V) = 0.15W
Even under worst-case conditions LTC3035’s BIAS pin
power dissipation is only about 1mW, thus can be
ignored. The junction to ambient thermal resistance will be
on the order of 76°C/W. The junction temperature rise
above ambient will be approximately equal to:
0.15W(76°C/W) = 11.4°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
T = 50°C + 11.4°C = 61.4°C
Short-Circuit/Thermal Protection
The LTC3035 has built-in output short-circuit current
limiting as well as over temperature protection. During
short-circuit conditions, internal circuitry automatically
limits the output current to approximately 760mA. At
higher temperatures, or in cases where internal power
dissipation causes excessive self heating on chip, the
thermal shutdown circuitry will shut down the charge
pump and LDO when the junction temperature exceeds
approximately 155°C. It will reenable the converter and
LDO once the junction temperature drops back to approxi-
mately 140°C. The LTC3035 will cycle in and out of
thermal shutdown without latch-up or damage until the
overstress condition is removed. Long term overstress
(T
J
>125°C) should be avoided as it can degrade the
performance or shorten the life of the part.
Layout Considerations
Connection from the BIAS and OUT pins to their respective
ceramic bypass capacitor should be kept as short as
possible. The ground side of the bypass capacitors should
be connected directly to the ground plane for best results
or through short traces back to the GND pin of the part.
Long traces will increase the effective series ESR and
inductance of the capacitor which can degrade
performance.
The CP and CM pins of the charge pump are switching
nodes. The transition edge rates of these pins can be quite
fast (~10ns). Thus care must be taken to make sure these
nodes do not couple capacitively to other nodes (espe-
cially the ADJ pin). Place the flying capacitor as close as
possible to the CP and CM pins for optimum charge pump
performance.
Because the ADJ pin is relatively high impedance
(depending on the resistor divider used), stray capaci-
tance at this pin should be minimized (<10pF) to prevent
phase shift in the error amplifier loop. Additional special
attention should be given to any stray capacitances that
can couple external signals onto the ADJ pin producing
undesirable output ripple. For optimum performance
connect the ADJ pin to R1 and R2 with a short PCB trace
and minimize all other stray capacitance to the ADJ pin.
Figure 7 shows an example layout for the LTC3035.
Figure 7. Suggested Layout
C
BIAS
BIAS
3035 F07
SHDN
OUT
ADJ
IN
GND
CM
CP
CF
R2
VIA CONNECTION
TO GND PLANE
R1
C
OUT
C
IN
4
3
2
1
5
6
7
8
