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MAX9257GTL/V+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
MAX9257/MAX9258
10 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
MAX9257 Pin Description
PIN
TQFN LQFP
NAME FUNCTION
1, 18 2, 21 V
CCIO
Single-Ended Input/Output Buffer Supply Voltage. Bypass V
CCIO
to GND with 0.1µF and
0.001µF capacitors in parallel as close as possible to the device with the smallest value
capacitor closest to V
CCIO
.
2, 11,
19, 34
3, 14,
22, 41
GND Digital Supply Ground
3–8 4–9
DIN[9:14]/
GPIO[1:6]
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits
word length, DIN_ not programmed as data inputs becomes GPIO (Table 22). DIN[9:14]
are internally pulled down to ground.
9 10 GND
FPLL
Filter PLL Ground
10 11 V
CCFPLL
Filter PLL Supply Voltage. Bypass V
CCFPLL
to GND
FPLL
with 0.1µF and 0.001µF capacitors
in parallel as close as possible to the device with the smallest value capacitor closest to
V
CCFPLL
.
12 15
DIN15/GPIO7
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits
word length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN15 is
internally pulled down to ground.
13 16
HSYNC_IN
Horizontal SYNC Input. HSYNC_IN is internally pulled down to ground.
14 17
VSYNC_IN
Vertical SYNC Input. VSYNC_IN is internally pulled down to ground.
15 18 PCLK_IN
Parallel Clock Input. PCLK_IN latches data and sync inputs and provides the PLL reference
clock. PCLK_IN is internally pulled down to ground.
16 19 SCL/TX
O p en- D r ai n C ontr ol C hannel Outp ut. S C L/TX b ecom es S C L outp ut w hen U ART- to- I
2
C i s
acti ve. S C L/TX b ecom es TX outp ut w hen U ART- to- I
2
C i s b yp assed . E xter nal l y p ul l up to V
C C
.
17 20 SDA/RX
Open-Drain Control Channel Input/Output. SDA/RX becomes bidirectional SDA when
UART-to-I
2
C is active. SDA/RX becomes RX input when UART-to-I
2
C is bypassed. SDA
output requires a pullup to V
CC
.
20, 33
23, 40 V
CC
Digital Supply Voltage. Bypass V
CC
to ground with 0.1µF and 0.001µF capacitors in p ar al l el
as cl ose as p ossi b l e to the d evi ce w i th the sm al l est val ue cap aci tor cl osest to V
C C
.
21 26 GPIO8 General Purpose Input/Output
22 27 GPIO9 General Purpose Input/Output
23 28 V
CCSPLL
Spread PLL Supply Voltage. Bypass V
CCSPLL
to GND
SPLL
with 0.1µF and 0.001µF
capacitors in parallel as close as possible to the device with the smallest value capacitor
closest to V
CCSPLL
.
24 29 GND
SPLL
SPLL Ground
25 30 GND
LVDS
LVDS Ground
26 31 SDO- Serial LVDS Inverting Output
27 32 SDO+ Serial LVDS Noninverting Output
28 33 V
CCLVDS
LVDS Supply Voltage. Bypass V
CCLVDS
to GND
LVDS
with 0.1µF and 0.001µF capacitors in
parallel as close as possible to the device with the smallest value capacitor closest to
V
CCLVDS
.
MAX9257/MAX9258
______________________________________________________________________________________ 11
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
MAX9257 Pin Description (continued)
PIN
TQFN LQFP
NAME FUNCTION
29 34 REM
Remote Power-Up/Power-Down Select Input. Connect REM to ground for power-up to
follow V
CC
. Connect REM high to V
CC
through 10k
Ω
resistor for remote power-up. REM is
internally pulled down to GND.
30, 31, 32,
35–39
35, 38,
39, 42–46
DIN[0:7] Data Inputs. DIN[0:7] are internally pulled down to ground.
40 47
DIN8/GPIO0
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits
word length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN8 is
internally pulled down to ground.
—
1, 12, 13
24, 25,
36, 37, 48
N.C. No Connection. Not internally connected.
— — EP Exposed Pad for Thin QFN Package Only. Connect EP to ground.
MAX9258 Pin Description
PIN NAME FUNCTION
1, 12, 13, 24,
25, 36,
37
N.C. No Connection. Not internally connected.
2V
CC
Digital Supply Voltage. Bypass V
CC
to GND with 0.1µF and 0.001µF capacitors in parallel as close
as possible to the device with the smallest value capacitor closest V
CC
.
3, 14 GND Digital Supply Ground
4 PD
LVCMOS/LVTTL Power-Down Input. Drive PD high to power up the device and enable all outputs.
Drive PD low to put all outputs in high impedance and reduce supply current. PD is internally pulled
down to ground.
5V
CCLVDS
LVDS Supply Voltage. Bypass V
CCLVDS
to GND
LVDS
with 0.1µF and 0.001µF capacitors in parallel
as close as possible to the device with the smallest value capacitor closest to V
CCLVDS
.
6 SDI- Serial LVDS Inverting Input
7 SDI+ Serial LVDS Noninverting Input
8 GND
LVDS
LVDS Supply Ground
9 GND
PLL
PLL Supply Ground
10 V
CCPLL
PLL Supply Voltage. Bypass V
CCPLL
to GND
PLL
with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to V
CCPLL
.
11 ERROR
Active-Low, Open-Drain Error Output. ERROR asserts low to indicate a data transfer error was
detected (parity, PRBS, or UART control channel error). ERROR is high to indicate no error detected.
ERROR resets when the error registers are read for parity, control channel errors, and when PRBS
enable bit is reset for PRBS errors. Pull up to V
CCOUT
with a 1kΩ resistor.
15 RX LVCMOS/LVTTL Control Channel UART Output
MAX9257/MAX9258
12 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
MAX9258 Pin Description (continued)
PIN NAME FUNCTION
16 TX LVCMOS/LVTTL Control Channel UART Input. TX is internally pulled up to V
CCOUT
.
17 LOCK
Open-Drain Lock Output. LOCK asserts high to indicate PLLs are locked with correct serial-word
boundary alignment. LOCK asserts low to indicate PLLs are not locked or incorrect serial-word
boundary alignment was detected. Pull up to V
CCOUT
with a 1k
Ω
resistor.
18
PCLK_OUT
LVCMOS/LVTTL Recovered Clock Output
19
VSYNC_OUT
LVCMOS/LVTTL Vertical SYNC Output
20
HSYNC_OUT
LVCMOS/LVTTL Horizontal SYNC Output
21, 28–35,
40–46
DOUT[15:0]
LVCMOS/LVTTL Data Outputs
22, 39 V
CCOUT
Output Supply Voltage. V
CCOUT
is the supply for all output buffers. Bypass V
CCOUT
to GND
OUT
with
0.1µF and 0.001µF capacitors in parallel as close as possible to the device with the smallest value
capacitor closest to V
CCOUT
.
23, 38, 48
GND
OUT
Output Supply Ground
26 V
CCSPLL
Spread-Spectrum PLL Supply Voltage. Bypass V
CCSPLL
to GND
SPLL
with 0.1µF and 0.001µF
capacitors in parallel as close as possible to the device with the smallest value capacitor closest to
V
CCSPLL
.
27 GND
SPLL
SPLL Ground
47 CCEN
LVCMOS/LVTTL Control Channel Enabled Output. CCEN asserts high to indicate that control
channel is enabled.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

MAX9257GTL/V+T

Mfr. #:
Buy MAX9257GTL/V+T
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes Prog Serializer / Deserializer
Lifecycle:
New from this manufacturer.
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