MAX9257/MAX9258
______________________________________________________________________________________ 13
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
SDO-
V
OD
V
OS
GND
R
L
/2
R
L
/2
SDO+
SDO-
SDO+
(SDO+) - (SDO-)
V
OS
(-) V
OS
(+)
((SDO+) + (SDO-))/2
V
OS
(-)
V
OD
(-)
V
OD
(-)
V
OD
= 0V
V
OS
= |V
OS
(+) - V
OS
(-)|
V
OD
= |V
OD
(+) - V
OD
(-)|
V
OD
(+)
Figure 1. MAX9257 LVDS DC Output Parameters
V
ID
= 0V
+V
ID
-V
ID
V
OUT
V
HYST+
V
HYST-
Figure 2. Input Hysteresis
PCLK_IN
NOTE: PCLK_IN PROGRAMMED FOR RISING LATCH EDGE.
DIN
Figure 3. MAX9257 Worst-Case Pattern Input
MAX9257/MAX9258
14 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
SDO-
C
L
C
L
R
L
SDO+
t
FALL
20%20%
(SDO+) - (SDO-)
80%
80%
t
RISE
Figure 4. MAX9257 LVDS Control Channel Output Load and Output Rise/Fall Times
V
IHMIN
V
IHMIN
V
IHMIN
V
ILMAX
V
ILMAX
V
ILMAX
PCLK_IN
DIN, VSYNC_IN, HSYNC_IN
t
HOLD
t
SET
NOTE: PCLK_IN PROGRAMMED FOR RISING LATCHING EDGE.
Figure 5. MAX9257 Input Setup and Hold Times
MAX9257/MAX9258
______________________________________________________________________________________ 15
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
t
PSD1
FIRST BIT LAST BIT
N
N+3
EXPANDED TIME SCALE
N+4
N
N+1
N+2
N-1
DIN, HSYNC_IN,
VSYNC_IN
PCLK_IN
SDO
Figure 6. MAX9257 Parallel-to-Serial Delay
V
ILMAX
t
HIGH
t
LOW
t
T
t
R
t
F
V
IHMIN
PCLK_IN
Figure 7. MAX9257 Parallel Input Clock Requirements
PCLK_OUT
DOUT
NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCH EDGE.
Figure 8. MAX9258 Worst-Case Pattern Output
0.9 x V
CCOUT
0.1 x V
CCOUT
t
F
t
R
C
L
SINGLE-ENDED OUTPUT LOAD
MAX9258
Figure 9. MAX9258 Output Rise and Fall Times

MAX9257GTL/V+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes Prog Serializer / Deserializer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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