© Semiconductor Components Industries, LLC, 2010
November, 2010 Rev. 9
1 Publication Order Number:
NLAST44599/D
NLAST44599
Low Voltage Single Supply
Dual DPDT Analog Switch
The NLAST44599 is an advanced CMOS dualindependent
DPDT (double poledouble throw) analog switch, fabricated with
silicon gate CMOS technology. It achieves highspeed propagation
delays and low ON resistances while maintaining CMOS lowpower
dissipation. This DPDT controls analog and digital voltages that may
vary across the full powersupply range (from V
CC
to GND).
The device has been designed so the ON resistance (R
ON
) is much
lower and more linear over input voltage than R
ON
of typical CMOS
analog switches.
The channelselect input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused
by supply voltage input/output voltage mismatch, battery backup,
hot insertion, etc.
The NLAST44599 can also be used as a quad 2to1 multiplexer
demultiplexer analog switch with two Select pins that each controls
two multiplexerdemultiplexers.
Select Pins Compatible with TTL Levels
Channel Select Input Overvoltage Tolerant to 5.5 V
Fast Switching and Propagation Speeds
BreakBeforeMake Circuitry
Low Power Dissipation: I
CC
= 2 A (Max) at T
A
= 25°C
Diode Protection Provided on Channel Select Input
Improved Linearity and Lower ON Resistance over Input Voltage
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model > 2000 V;
Machine Model > 100 V
Chip Complexity: 158 FETs
PbFree Packages are Available
MARKING
DIAGRAMS
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
QFN16
MN SUFFIX
CASE 485G
TSSOP16
DT SUFFIX
CASE 948F
1
T
ALYWG
G
16
http://onsemi.com
1
16
NLAT
4459
ALYWG
G
1
16
(Note: Microdot may be in either location)
NLAST44599
http://onsemi.com
2
QFN16 PACKAGE
1
23
7568
9101112
13141516
COM A
NO A
0
V
CC
NC D
1
NC A
1
SAB
NO B
0
COM B
NC B1
GND
NO C
0
COM C
See TSSOP16
Switch Configuration
COM D
NO D
0
SCD
NC C
1
4
FUNCTION TABLE
Select AB or CD ON Channel
L
H
NC to COM
NO to COM
V
CC
NC D1
COM D
NO D0
SELECT CD
NC C
1
COM C
NO C
0
NC B
1
GND
NO B
0
COM B
NC A
1
COM A
NO A
0
E
LECT AB
116
2
3
4
5
6
7
8
9
10
11
12
13
14
15
U
U
COM A
SELECT AB X1
NO A
0
U
NC A
1
Figure 1. Logic Diagram
TSSOP16 PACKAGE
U
NO B
0
U
NC B
1
U
NO C
0
U
NC C
1
U
NO D
0
U
NC D
1
SELECT CD X1
U
COM B
U
COM C
U
COM D
0/1
2/3
0/1
2/3
0
1
2
3
0
1
2
3
Figure 2. IEC Logic Symbol
NLAST44599
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
Positive DC Supply Voltage *0.5 to )7.0 V
V
IS
Analog Input Voltage (V
NO
or V
COM
) *0.5 V
IS
V
CC
)0.5 V
V
IN
Digital Select Input Voltage *0.5 V
I
)7.0 V
I
IK
DC Current, Into or Out of Any Pin $50 mA
P
D
Power Dissipation in Still Air QFN16
TSSOP16
800
450
mW
T
STG
Storage Temperature Range *65 to )150 °C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
T
J
Junction Temperature Under Bias +150 °C
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% 35% UL94VO (0.125 in)
V
ESD
ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
2000
100
1000
V
I
LATCHUP
LatchUp Performance Above V
CC
and Below GND at 125°C (Note 4) $300 mA
JA
Thermal Resistance QFN16
TSSOP16
80
164
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22A114A.
2. Tested to EIA/JESD22A115A.
3. Tested to JESD22C101A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
IN
Digital Select Input Voltage GND 5.5 V
V
IS
Analog Input Voltage (NC, NO, COM) GND V
CC
V
T
A
Operating Temperature Range *55 )125 °C
t
r
, t
f
Input Rise or Fall Time, SELECT V
CC
= 3.3 V $ 0.3 V
V
CC
= 5.0 V $ 0.5 V
0
0
100
20
ns/V
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100
1000
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time Junction Temperature
NORMALIZED FAILURE RATE
TIME, YEARS
T
J
= 130°C
T
J
= 120°C
T
J
= 110°C
T
J
= 100°C
T
J
= 90°C
T
J
= 80°C

NLAST44599MN

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC SWITCH DUAL DPDT 16QFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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