MAX1444
10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
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The MAX1444 provides three modes of reference oper-
ation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, the internal reference out-
put (REFOUT) can be connected to the REFIN pin
through a resistor (e.g., 10kΩ) or resistor-divider if an
application requires a reduced full-scale range. For sta-
bility purposes, it is recommended to bypass REFIN
with a >10nF capacitor to GND.
In buffered external reference mode, the reference vol-
tage levels can be adjusted externally by applying a
stable and accurate voltage at REFIN. In this mode,
REFOUT may be left open or connected to REFIN
through a >10kΩ resistor.
In unbuffered external reference mode, REFIN is con-
nected to GND, thereby deactivating the on-chip
buffers of REFP, COM, and REFN. With their buffers
shut down, these pins become high impedance inputs
and can be driven by external reference sources.
Clock Input (CLK)
The MAX1444 CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the falling edge of the clock signal,
mandating this edge to provide lowest possible jitter.
Any significant aperture jitter would limit the SNR per-
formance of the ADC as follows:
SNR = 20log (1 / 2πf
IN
t
AJ
)
where f
IN
represents the analog input frequency, and
t
AJ
is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1444 clock input operates with a voltage
threshold set to V
DD
/2. Clock inputs with a duty cycle
other than 50% must meet the specifications for high
and low periods as stated in the
Electrical Character-
istics
. See Figures 3a, 3b, 4a, and 4b for the relation-
ship between spurious-free dynamic range (SFDR),
signal-to-noise ratio (SNR), total harmonic distortion
(THD), or signal-to-noise plus distortion (SINAD) versus
clock duty cycle.
Output Enable (
OE
), Power Down (PD),
and Output Data (D0–D9)
All data outputs, D0 (LSB) through D9 (MSB), are
TTL/CMOS-logic compatible. There is a 5.5 clock-cycle
latency between any particular sample and its valid
output data. The output coding is straight offset binary
(Table 1). With OE and PD (power down) high, the digi-
tal output enters a high-impedance state. If OE is held
low with PD high, the outputs are latched at the last
value prior to the power down.
The capacitive load on the digital outputs D0–D9
should be kept as low as possible (<15pF) to avoid
large digital currents that could feed back into the ana-
log portion of the MAX1444, thus degrading its dynam-
ic performance. The use of buffers on the ADC’s digital
outputs can further isolate the digital outputs from
heavy capacitive loads.
Figure 5 displays the timing relationship between out-
put enable and data output valid as well as power-
down/wake-up and data output valid.
Table 1. MAX1444 Output Code for Differential Inputs
