1 MSPS, 12-/10-/8-Bit ADCs
in 6-Lead SOT-23
AD7476/AD7477/AD7478
Rev. F
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FEATURES
Fast throughput rate: 1 MSPS
Specified for V
DD
of 2.35 V to 5.25 V
Low power
3.6 mW at 1 MSPS with 3 V supplies
15 mW at 1 MSPS with 5 V supplies
Wide input bandwidth
70 dB SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Standby mode: 1 μA maximum
6-lead SOT-23 package
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
FUNCTIONAL BLOCK DIAGRAM
01024-001
CONTROL
LOGIC
12-/10-/8-BIT
SUCCESSIVE-
APPROXIMATION
ADC
V
IN
SCLK
SDATA
CS
V
DD
GND
AD7476/AD7477/AD7478
Figure 1.
GENERAL DESCRIPTION
The AD7476/AD7477/AD7478
1
are, respectively, 12-bit, 10-bit,
and 8-bit, high speed, low power, successive approximation
ADCs. The parts operate from a single 2.35 V to 5.25 V power
supply and feature throughput rates up to 1 MSPS. Each part
contains a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 6 MHz.
The conversion process and data acquisition are controlled
using
CS
and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
CS
and the conversion is initiated at this
point. There are no pipeline delays associated with these parts.
The AD7476/AD7477/AD7478 use advanced design techniques
to achieve very low power dissipation at high throughput rates.
The reference for the parts is taken internally from V
DD
. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the parts are 0 V to V
DD
. The conversion
rate is determined by the SCLK.
1
Protected by U.S. Patent No. 6,681,332.
PRODUCT HIGHLIGHTS
1. First 12-/10-/8-Bit ADCs in SOT-23 Packages.
2. High Throughput with Low Power Consumption.
3. Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced while not converting. The parts also feature a
shutdown mode to maximize power efficiency at lower
throughput rates. Current consumption is 1 A maximum
when in shutdown mode.
4. Reference Derived from the Power Supply.
5. No Pipeline Delay. The parts feature a standard successive-
approximation ADC with accurate control of the sampling
instant via a
CS
input and once-off conversion control.
AD7476/AD7477/AD7478
Rev. F | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AD7476 Specifications ................................................................. 3
AD7477 Specifications ................................................................. 5
AD7478 Specifications ................................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Circuit Information .................................................................... 13
Converter Operation .................................................................. 13
ADC Transfer Function ............................................................. 13
Typical Connection Diagram ................................................... 14
Modes of Operation ................................................................... 15
Power vs. Throughput Rate ....................................................... 17
Serial Interface ............................................................................ 18
Microprocessor Interfacing ....................................................... 19
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
1/09—Rev. E to Rev. F
Changes to Features .......................................................................... 1
Changes to Ordering Guide .......................................................... 22
4/06—Rev. D to Rev. E
Updated Format .................................................................. Universal
Changes to Table 1 Endnotes .......................................................... 3
Changes to Table 2 Endnotes .......................................................... 5
Changes to Table 3 Endnotes .......................................................... 7
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
3/04—Rev. C to Rev. D
Added U.S. Patent Number .............................................................. 1
Changes to Specifications ................................................................. 2
Changes to Absolute Maximum Ratings ........................................ 6
Changes to AD7476/AD7477/AD7478 to ADSP-21xx
Interface section .............................................................................. 16
2/03—Rev. B to Rev. C
Changes to General Description ..................................................... 1
Changes to Specifications ................................................................. 2
Changes to Absolute Maximum Ratings ........................................ 6
Changes to Ordering Guide ............................................................. 6
Changes to Typical Connection Diagram section ..................... 10
Changes to Figure 8 caption .......................................................... 11
Changes to Figure 19 ...................................................................... 16
Changes to Figure 20 ...................................................................... 17
Updated Outline Dimensions ....................................................... 18
AD7476/AD7477/AD7478
Rev. F | Page 3 of 24
SPECIFICATIONS
AD7476 SPECIFICATIONS
A version: V
DD
= 2.7 V to 5.25 V, f
SCLK
= 20 MHz, f
SAMPLE
= 1 MSPS, unless otherwise noted; S and B versions: V
DD
= 2.35 V to 5.25 V,
f
SCLK
= 12 MHz, f
SAMPLE
= 600 kSPS, unless otherwise noted; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter A Version
1,2
B Version
1,2
S Version
1,2
Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f
IN
= 100 kHz sine wave
Signal-to-(Noise + Distortion) (SINAD)
3
69 70 69 dB min B version, V
DD
= 2.4 V to 5.25 V
70 70 dB min T
A
= 25°C
71.5 dB typ
Signal-to-Noise Ratio (SNR)
3
70 71 70 dB min B version, V
DD
= 2.4 V to 5.25 V
72.5 dB typ
Total Harmonic Distortion (THD)
3
−80 −78 −78 dB typ
Peak Harmonic or Spurious Noise (SFDR)
3
−82 −80 −80 dB typ
Intermodulation Distortion (IMD)
3
Second-Order Terms −78 −78 −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz
Third-Order Terms −78 −78 −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz
Aperture Delay 10 10 10 ns typ
Aperture Jitter 30 30 30 ps typ
Full Power Bandwidth 6.5 6.5 6.5 MHz typ @ 3 dB
DC ACCURACY S, B versions, V
DD
= (2.35 V to 3.6 V)
4
;
A version, V
DD
= (2.7 V to 3.6 V)
Resolution 12 12 12 Bits
Integral Nonlinearity
3
±1.5 ±1.5 LSB max
±1 ±0.6 ±0.6 LSB typ
Differential Nonlinearity
3
−0.9/+1.5 −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits
±0.75 ±0.75 ±0.75 LSB typ
Offset Error
3
±1.5 ±2 LSB max
±0.5 LSB typ
Gain Error
3
±1.5 ±2 LSB max
±0.5 LSB typ
ANALOG INPUT
Input Voltage Ranges 0 to V
DD
0 to V
DD
0 to V
DD
V
DC Leakage Current ±1 ±1 ±1 μA max
Input Capacitance 30 30 30 pF typ
LOGIC INPUT
Input High Voltage, V
INH
2.4 2.4 2.4 V min
1.8 1.8 1.8 V min V
DD
= 2.35 V
Input Low Voltage, V
INL
0.4 0.4 0.4 V max V
DD
= 3 V
0.8 0.8 0.8 V max V
DD
= 5 V
Input Current, I
IN
, SCLK Pin ±1 ±1 ±1 μA max Typically 10 nA, V
IN
= 0 V or V
DD
Input Current, I
IN
, CS Pin
±1 ±1 ±1 μA typ
Input Capacitance, C
IN
5
10 10 10 pF max
LOGIC OUTPUT
Output High Voltage, V
OH
V
DD
− 0.2 V
DD
− 0.2 V
DD
− 0.2 V min I
SOURCE
= 200 μA; V
DD
= 2.35 V to 5.25 V
Output Low Voltage, V
OL
0.4 0.4 0.4 V max I
SINK
= 200 μA
Floating-State Leakage Current ±10 ±10 ±10 μA max
Floating-State Output Capacitance
5
10 10 10 pF max
Output Coding Straight (Natural) Binary

AD7477ARTZ-500RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10Bit 1MSPS Lo-Pwr
Lifecycle:
New from this manufacturer.
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