AD7476/AD7477/AD7478
Rev. F | Page 8 of 24
Parameter A Version
1,2
S Version
1,2
Unit Test Conditions/Comments
Power Dissipation
5
Normal Mode (Operational) 17.5 17.5 mW max V
DD
= 5 V, f
SAMPLE
= 1 MSPS
4.8 4.8 mW max V
DD
= 3 V, f
SAMPLE
= 1 MSPS
Full Power-Down 5 5 μW max V
DD
= 5 V, SCLK off
1
Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C.
2
Operational from V
DD
= 2.0 V, with input high voltage, V
INH
= 1.8 V minimum.
3
See the Terminology section.
4
Guaranteed by characterization.
5
See the Power vs. Throughput Rate section.
TIMING SPECIFICATIONS
V
DD
= 2.35 V to 5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Limit at T
MIN
, T
MAX
1
Parameter
2, 3
3 V 5 V Unit Description
f
SCLK
4
10 10 kHz min
20 20
MHz
max
A version
12 12
MHz
max
B version
t
CONVERT
16 × t
SCLK
16 × t
SCLK
t
QUIET
50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion
t
1
10 10 ns min
Minimum CS
pulsewidth
t
2
10 10 ns min
CS
to SCLK setup time
t
3
5
20 20 ns max
Delay from CS
until SDATA three-state disabled
t
4
5
40 20 ns max Data access time after SCLK falling edge, A version
70 20 ns max Data access time after SCLK falling edge, B version
t
5
0.4 ×
t
SCLK
0.4 ×
t
SCLK
ns min SCLK low pulsewidth
t
6
0.4 ×
t
SCLK
0.4 ×
t
SCLK
ns min SCLK high pulsewidth
t
7
10 10 ns min SCLK to data valid hold time
t
8
6
10 10 ns min SCLK falling edge to SDATA high impedance
25 25 ns max SCLK falling edge to SDATA high impedance
t
POWER-UP
7
1 1 μs typ Power-up time from full power-down
1
3 V specifications apply from V
DD
= 2.7 V to 3.6 V for A version; 3 V specifications apply from V
DD
= 2.35 V to 3.6 V for B version; 5 V specifications apply from
V
DD
= 4.75 V to 5.25 V.
2
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
3
Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version.
4
Mark/space ratio for the SCLK input is 40/60 to 60/40.
5
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
6
t
8
is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to
remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, is the true bus relinquish time of the part and is independent of the bus
loading.
7
See Power-Up Time section.
01024-002
200µA I
OL
200µA I
OH
1.6
TO OUTPUT
PIN
C
L
50pF
Figure 2. Load Circuit for Digital Output Timing Specifications
