CIII51001-2.4
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Cyclone III Device Handbook
Volume 1
July 2012
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1. Cyclone III Device Family Overview
Cyclone
®
III device family offers a unique combination of high functionality, low
power and low cost. Based on Taiwan Semiconductor Manufacturing Company
(TSMC) low-power (LP) process technology, silicon optimizations and software
features to minimize power consumption, Cyclone III device family provides the ideal
solution for your high-volume, low-power, and cost-sensitive applications. To address
the unique design needs, Cyclone III device family offers the following two variants:
Cyclone III—lowest power, high functionality with the lowest cost
Cyclone III LS—lowest power FPGAs with security
With densities ranging from about 5,000 to 200,000 logic elements (LEs) and
0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power
consumption, Cyclone III device family makes it easier for you to meet your power
budget. Cyclone III LS devices are the first to implement a suite of security features at
the silicon, software, and intellectual property (IP) level on a low-power and
high-functionality FPGA platform. This suite of security features protects the IP from
tampering, reverse engineering and cloning. In addition, Cyclone III LS devices
support design separation which enables you to introduce redundancy in a single
chip to reduce size, weight, and power of your application.
This chapter contains the following sections:
“Cyclone III Device Family Features” on page 1–1
“Cyclone III Device Family Architecture” on page 1–6
“Reference and Ordering Information” on page 1–12
Cyclone III Device Family Features
Cyclone III device family offers the following features:
Lowest Power FPGAs
Lowest power consumption with TSMC low-power process technology and
Altera
®
power-aware design flow
Low-power operation offers the following benefits:
Extended battery life for portable and handheld applications
Reduced or eliminated cooling system costs
Operation in thermally-challenged environments
Hot-socketing operation support
July 2012
CIII51001-2.4
1–2 Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Features
Cyclone III Device Handbook July 2012 Altera Corporation
Volume 1
Design Security Feature
Cyclone III LS devices offer the following design security features:
Configuration security using advanced encryption standard (AES) with 256-bit
volatile key
Routing architecture optimized for design separation flow with the Quartus
®
II
software
Design separation flow achieves both physical and functional isolation
between design partitions
Ability to disable external JTAG port
Error Detection (ED) Cycle Indicator to core
Provides a pass or fail indicator at every ED cycle
Provides visibility over intentional or unintentional change of configuration
random access memory (CRAM) bits
Ability to perform zeroization to clear contents of the FPGA logic, CRAM,
embedded memory, and AES key
Internal oscillator enables system monitor and health check capabilities
Increased System Integration
High memory-to-logic and multiplier-to-logic ratio
High I/O count, low-and mid-range density devices for user I/O constrained
applications
Adjustable I/O slew rates to improve signal integrity
Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X,
LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS
Supports the multi-value on-chip termination (OCT) calibration feature to
eliminate variations over process, voltage, and temperature (PVT)
Four phase-locked loops (PLLs) per device provide robust clock management and
synthesis for device clock management, external system clock management, and
I/O interfaces
Five outputs per PLL
Cascadable to save I/Os, ease PCB routing, and reduce jitter
Dynamically reconfigurable to change phase shift, frequency multiplication or
division, or both, and input frequency in the system without reconfiguring the
device
Remote system upgrade without the aid of an external controller
Dedicated cyclical redundancy code checker circuitry to detect single-event upset
(SEU) issues
Nios
®
II embedded processor for Cyclone III device family, offering low cost and
custom-fit embedded processing solutions
Chapter 1: Cyclone III Device Family Overview 1–3
Cyclone III Device Family Features
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 1
Wide collection of pre-built and verified IP cores from Altera and Altera
Megafunction Partners Program (AMPP) partners
Supports high-speed external memory interfaces such as DDR, DDR2,
SDR SDRAM, and QDRII SRAM
Auto-calibrating PHY feature eases the timing closure process and eliminates
variations with PVT for DDR, DDR2, and QDRII SRAM interfaces
Cyclone III device family supports vertical migration that allows you to migrate your
device to other devices with the same dedicated pins, configuration pins, and power
pins for a given package-across device densities. This allows you to optimize device
density and cost as your design evolves.
Table 11 lists Cyclone III device family features.
Table 1–1. Cyclone III Device Family Features
Family Device
Logic
Elements
Number of
M9K
Blocks
Total RAM
Bits
18 x 18
Multipliers
PLLs
Global
Clock
Networks
Maximum
User I/Os
Cyclone III
EP3C5 5,136 46 423,936 23 2 10 182
EP3C10 10,320 46 423,936 23 2 10 182
EP3C16 15,408 56 516,096 56 4 20 346
EP3C25 24,624 66 608,256 66 4 20 215
EP3C40 39,600 126 1,161,216 126 4 20 535
EP3C55 55,856 260 2,396,160 156 4 20 377
EP3C80 81,264 305 2,810,880 244 4 20 429
EP3C120 119,088 432 3,981,312 288 4 20 531
Cyclone III
LS
EP3CLS70 70,208 333 3,068,928 200 4 20 429
EP3CLS100 100,448 483 4,451,328 276 4 20 429
EP3CLS150 150,848 666 6,137,856 320 4 20 429
EP3CLS200 198,464 891 8,211,456 396 4 20 429

EP3C16F256C6

Mfr. #:
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array FPGA - Cyclone III 963 LABs 168 IOs
Lifecycle:
New from this manufacturer.
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