Chapter 1: Cyclone III Device Family Overview 1–13
Document Revision History
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 1
Document Revision History
Table 17 lists the revision history for this document.
Table 1–7. Document Revision History
Date Version Changes
July 2012 2.4 Updated 484 pin package code in Figure 1–1.
December 2011 2.3
Updated Table 1–1 and Table 1–2.
Updated Figure 1–1 and Figure 1–2.
Updated hyperlinks.
Minor text edits.
December 2009 2.2 Minor text edits.
July 2009 2.1 Minor edit to the hyperlinks.
June 2009 2.0
Added Table 1–5.
Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4.
Updated “Introduction”, “Cyclone III Device Family Architecture”, “Embedded Multipliers
and Digital Signal Processing Support ”, “Clock Networks and PLLs ”, “I/O Features ”,
“High-Speed Differential Interfaces ”, “Auto-Calibrating External Memory Interfaces ”,
“Quartus II Software Support”, “Configuration ”, and “Design Security (Cyclone III LS
Devices Only)”.
Removed “Referenced Document” section.
October 2008 1.3
Updated “Increased System Integration” section.
Updated “Memory Blocks” section.
Updated chapter to new template.
May 2008 1.2
Added 164-pin Micro FineLine Ball-Grid Array (MBGA) details to Table 1–2, Table 1–3 and
Table 1–4.
Updated Figure 1–2 with automotive temperature information.
Updated “Increased System Integration” section, Table 1–6, and “High-Speed Differential
Interfaces” section with BLVDS information.
July 2007 1.1
Removed the text “Spansion” in “Increased System.
Integration” and “Configuration” sections.
Removed trademark symbol from “MultiTrack” in “MultiTrack Interconnect”.
Removed registered trademark symbol from “Simulink” and “MATLAB” from “Embedded
Multipliers and Digital.
Signal Processing Support” section.
Added chapter TOC and “Referenced Documents” section.
March 2007 1.0 Initial release.
1–14 Chapter 1: Cyclone III Device Family Overview
Document Revision History
Cyclone III Device Handbook July 2012 Altera Corporation
Volume 1

EP3C16F256C6

Mfr. #:
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array FPGA - Cyclone III 963 LABs 168 IOs
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