AD7849
Rev. C | Page 11 of 20
CIRCUIT DESCRIPTION
DIGITAL-TO-ANALOG CONVERSION
Figure 15 shows the digital-to-analog section of the AD7849. There
are three on-chip DACs, each of which has its own buffer amplifier.
DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor string,
but they have their own analog multiplexers. The voltage reference
is applied to the resistor string. DAC3 is a 12-bit voltage mode
DAC with its own output stage.
The four MSBs of the 16-bit digital input code drive DAC1 and
DAC2, while the 12 LSBs control DAC3. Using DAC1 and DAC2,
the MSBs select a pair of adjacent nodes on the resistor string
and present that voltage to the positive and negative inputs of
DAC3. This DAC interpolates between these two voltages to
produce the analog output voltage.
To prevent nonmonotonicity in the DAC due to amplifier offset
voltages, DAC1 and DAC2 leap-frog along the resistor string.
For example, when switching from Segment 1 to Segment 2, DAC1
switches from the bottom of Segment 1 to the top of Segment 2
while DAC 2 remains connected to the top of Segment 1. The
code driving DAC3 is automatically complemented to compensate
for the inversion of its inputs. This means that any linearity
effects due to amplifier offset voltages remain unchanged when
switching from one segment to the next, and 16-bit monotonicity is
ensured if DAC3 is monotonic. Therefore, 12-bit resistor matching
in DAC3 guarantees overall 16-bit monotonicity. This is much
more achievable than the 16-bit matching that a conventional
R-2R structure would need.
Output Stage
The output stage of the AD7849 is shown in Figure 14. It is capable
of driving a 2 kΩ load in parallel with 200 pF. The feedback and
offset resistors allow the output stage to be configured for gains of
1 or 2. Additionally, the offset resistor can be used to shift the
output range. The AD7849 has a special feature to ensure output
stability during power-up and power-down sequences. This feature
is available for control applications where actuators must not be
allowed to move in an uncontrolled fashion.
LOGIC
CIRCUITRY
ONE-SHOT
LDAC
DAC 3
G3
C1
R
10kΩ
R
10kΩ
R
OFS
RSTIN
G1
V
OUT
AGND
RSTOUT
G2
VOLTAGE
MONITOR
01008-015
Figure 14. Output Stage
When the supply voltages are changing, the V
OUT
pin is clamped
to 0 V via a low impedance path. To prevent the output of A3
from being shorted to 0 V during this time, Transmission Gate G1
is opened. These conditions are maintained until the power
supplies stabilize, and a valid word is written to the DAC register.
At this time, G2 opens and G1 closes. Both transmission gates
are also externally controllable via the reset in (
RSTIN
) control
input. For instance, if the
RSTIN
input is driven from a battery
supervisor chip, then at power-off or during a brownout, the
RSTIN
input will be driven low to open G1 and closeG2. The
DAC has to be reloaded, with
RSTIN
high, to reenable the output.
Conversely, the on-chip voltage detector output (
RSTOUT
) is
also available to the user to control other parts of the system.
The AD7849 output buffer is configured as a track-and-hold
amplifier. Although normally tracking its input, this amplifier
isplaced in hold mode for approximately 5 μs after the leading
edge of
LDAC
. This short state keeps the DAC output at its
previous voltage while the is internally changing to its
new value. therefore, any glitches that occur in the transition are
not seen at the output. In systems where
AD7849
LDAC
is permanently
low, deglitching is not in operation.
10/12
DAC 2
A1
A2
DAC 3
10-BIT/12-BIT
DAC
S2
S4
S14
S16
DB15 TO DB12
DB15 TO DB12
DAC 1
S1
S3
S15
S17
REF+
V
REF–
OUTPUT
STAGE
R
R
R
R
R
R
01008-016
Figure 15. Digital-to-Analog Conversion
