AD7849
Rev. C | Page 16 of 20
Figure 26 shows the
LDAC
input of the being driven
from another bit programmable port line (PC1). As a result, the
DAC can be updated by taking
AD7849
LDAC
low after the DAC input
register has been loaded.
AD7849-to-TMS320C2x Interface
Figure 25 shows a serial interface between the AD7849 and the
TMS320C2x DSP processor. In this interface, the CLKX and
FSX signals for the TMS320C2x should be generated using
external clock/timer circuitry. The FSX pin of the TMS320C2x
must be configured as an input. Data from the TMS320C2x is
valid on the falling edge of CLKX.
68HC11*
PC0
SCK
MOSI
PC1
AD7849*
LDAC
SCLK
SDIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
01008-025
TMS320C2x
FSX
CLKX
DX
AD7849*
LDAC
SCLK
SDIN
SYNC
ADDITIONAL PINS OMITTED FOR CLARITY.
CLOCK/TIMER
01008-030
Figure 26. AD7849-to-68HC11 Interface
AD7849-to-87C51 Interface
A serial interface between the AD7849 and the 87C51
microcontroller is shown in Figure 27. TXD of the 87C51 drives
SCLK of the AD7849, while RXD drives the serial data line of
the part. The
SYNC
signal is derived from the P3.3 port line,
and the
LDAC
line is driven from the P3.2 port line.
Figure 25. AD7849-to-TMS320C2x Interface
The clock/timer circuitry generates the
LDAC
signal for the
to synchronize the update of the output with the serial
transmission. Alternatively, the automatic update mode can be
selected by connecting
AD7849
LDAC
to DGND.
The 87C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. Therefore, ensure that the data in the
SBUF register is arranged correctly so that the most significant
bits are the first to be transmitted to the AD7849, and the last
bit to be sent is the LSB of the word to be loaded to the AD7849.
When data is transmitted to the part, P3.3 is taken low. Data on
RXD is valid on the falling edge of TXD. The 87C51 transmits
its serial data in 8-bit bytes, with only eight falling clock edges
occurring in the transmit cycle. To load data to the AD7849, P3.3 is
left low after the first eight bits are transferred, and a second byte of
data is then transferred serially to the AD7849. When the second
serial transfer is complete, the P3.3 line is taken high.
AD7849-to-68HC11 Interface
Figure 26 shows a serial interface between the AD7849 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7849, while the MOSI output drives the serial data line
of the AD7849. The
SYNC
signal is derived from a port line
(PC0 shown).
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is transmitted to the part, PC0 is taken low. When
the 68HC11 is configured like this, data on MOSI is valid on the
falling edge of SCK. The 68HC11 transmits its serial data in 8-bit
bytes with only eight falling clock edges occurring in the transmit
cycle. To load data to the AD7849, PC0 is left low after the first
eight bits are transferred, and a second byte of data is then
transferred serially to the AD7849. When the second serial
transfer is complete, the PC0 line is taken high.
Figure 27 shows the
LDAC
input of the driven from
the bit programmable P3.2 port line. As a result, the DAC output
can be updated by taking the
AD7849
LDAC
line low following the
completion of the write cycle. Alternatively,
LDAC
can be
hardwired low, and the analog output is updated on the 16th
falling edge of TXD after the
SYNC
signal for the DAC goes low.
87C51*
P3.3
TXD
RXD
P3.2
AD7849*
LDAC
SCLK
SDIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
01008-026
Figure 27. AD7849-to-87C51 Interface
