AD7849
Rev. C | Page 14 of 20
Unipolar Configuration
Figure 20 shows the AD7849 in the unipolar binary circuit
configuration. The DAC is driven by the AD586, 5 V reference.
Because R
OFS
is tied to 0 V, the output amplifier has a gain of ×2,
and the output range is 0 V to 10 V. If a 0 V to 5 V range is
required, R
OFS
should be tied to V
OUT
, configuring the output
stage for a gain of ×1. Table 7 gives the code table for the circuit
shown in Figure 20.
R
OFS
V
DD
V
CC
V
REF+
V
OUT
V
OUT
(0V TO 10V)
AGND
V
REF–
V
SS
–15V
AD7849*
R1
10kΩ
AD586
C1
1nF
SIGNAL GND
6
8
4
5
*
ADDITIONAL PINS OMITTED FOR CLARITY.
2
DGND
+15
+5
01008-021
Figure 20. Unipolar Binary Operation
Table 7. Code Table for Figure 20
Binary Number in DAC Latch
MSB LSB Analog Output (V
OUT
)
1111 1111 1111 1111 10 (65,535/65,536) V
1000 0000 0000 0000 10 (32,768/65,536) V
0000 0000 0000 0001 10 (1/65,536) V
0000 0000 0000 0000 0 V
Table 7 assumes a 16-bit resolution; 1 LSB = 10 V/2
16
=
10 V/65,536 = 152 μV.
Offset and gain can be adjusted in Figure 20 as follows:
• To adjust offset, disconnect the V
REF−
input from 0 V, load the
DAC with all 0s, and adjust the V
REF−
voltage until V
OUT
= 0 V.
• To adjust gain, load the AD7849 with all 1s and adjust R1
until V
OUT
= 10 (65,535/65,536) = 9.9998474 V for the 16-bit,
B and C versions. For the 14-bit A version, V
OUT
should be
10 (16,383/16,384) = 9.9993896 V.
If a simple resistor divider is used to vary the V
REF−
voltage, it is
important that the temperature coefficients of these resistors
match that of the DAC input resistance (−300 ppm/°C). Otherwise,
extra offset errors will be introduced over temperature. Many
circuits do not require these offset and gain adjustments. In
these circuits, R1 can be omitted. Pin 5 of the AD586 may be
left open circuit, and Pin 2 (V
REF−
) of the AD7849 tied to 0 V.
Bipolar Configuration
Figure 21 shows the AD7849 set up for ±10 V bipolar operation.
The AD588 provides precision ±5 V tracking outputs that are
fed to the V
REF+
and V
REF−
inputs of the AD7849.The code table
for the circuit shown in Figure 21 is shown in Table 8.
Full-scale and bipolar-zero adjustment are provided by varying
the gain and balance on the AD588. R2 varies the gain on the
AD588, while R3 adjusts the +5 V and −5 V outputs together
with respect to ground.
V
OUT
(–10V TO +10V)
+15
+5
V
DD
V
CC
V
REF+
V
OUT
R
OFS
AGND
DGNDV
REF–
V
SS
–15V
AD7849*
SIGNAL
GND
*ADDITIONAL PINS OMITTED FOR CLARITY
AD588
C1
1µF
R2
100kΩ
R3
100kΩ
R1
39kΩ
6
15
2
8
5
14
7
9
3
1
10
12
11
4
13
16
01008-022
Figure 21. Bipolar ±10 V Operation
Table 8. Code Table for Figure 21
Binary Number in DAC Latch
MSB LSB Analog Output (V
OUT
)
1111 1111 1111 1111 +10 (32,767/32,768) V
1000 0000 0000 0001 +10 (1/32,768) V
1000 0000 0000 0001 0 V
0111 1111 1111 1111 −10 (1/32,768) V
0000 0000 0000 0000 −10 (32,768/32,768) V
Table 8 assumes a 16-bit resolution; 1 LSB = 20 V/2
16
= 305 μV.
For bipolar-zero adjustment on the AD7849, load the DAC with
100 … 000 and adjust R3 until V
OUT
= 0 V. Full scale is adjusted
by loading the DAC with all 1s and adjusting R2 until V
OUT
=
9.999694 V.
When bipolar-zero and full-scale adjustment are not needed,
omit R2 and R3, connect Pin 11 to Pin 12 on the AD588 and
leave Pin 5 on the AD588 floating.
If a ±5 V output range is desired with the circuit shown in
Figure 21, tie Pin 20 (R
OFS
) to Pin 19 (V
OUT
), thus reducing the
output gain stage to unity and giving an output range of ±5 V.
