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AD7849ARZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD7849
Rev. C | Page 3 of 20
SPECIFICATIONS
V
DD
= 14.25 V to 15.75 V; V
SS
= −14.25 V to −15.75 V; V
CC
= 4.75 V to 5.25 V; V
OUT
loaded with 2 kΩ, 200 pF to 0 V; V
REF+
= 5 V; R
OFS
connected to 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Temperature range for A, B, C versions is −40°C to +85°C.
Table 1.
Parameter A Version B Version C Version Unit Test Conditions/Comments
RESOLUTION 14 16 16 Bits
A version: 1 LSB = 2 (V
REF+
− V
REF−
)/2
14
;
B, C versions: 1 LSB = 2 (V
REF+
− V
REF−
)/2
16
UNIPOLAR OUTPUT V
REF−
= 0 V, V
OUT
= 0 V to 10 V
Relative Accuracy at 25°C ±4 ±6 ±4 LSB typ
T
MIN
to T
MAX
±5 ±16 ±8 LSB max
Differential Nonlinearity ±0.25 ±0.9 ±0.5 LSB max
All grades guaranteed monotonic
over temperature
Gain Error at 25°C ±1 ±4 ±4 LSB typ V
OUT
load = 10 MΩ
T
MIN
to T
MAX
±4 ±16 ±16 LSB max
Offset Error at 25°C ±1 ±4 ±4 LSB typ
T
MIN
to T
MAX
±6 ±24 ±16 LSB max
Gain Temperature Coefficient
1
±2 ±2 ±2
ppm FSR/
°C typ
Offset Temperature Coefficient
1
±2 ±2 ±2
ppm FSR/
°C typ
BIPOLAR OUTPUT V
REF−
= 5 V, V
OUT
= −10 V to +10 V
Relative Accuracy at 25°C ±2 ±3 ±2 LSB typ
T
MIN
to T
MAX
±3 ±8 ±4 LSB max
Differential Nonlinearity ±0.25 ±0.9 ±0.5 LSB max
All grades guaranteed monotonic
over temperature
Gain Error at 25°C ±1 ±4 ±4 LSB typ V
OUT
load = 10 MΩ
T
MIN
to T
MAX
±4 ±16 ±16 LSB max
Offset Error at 25°C ±0.5 ±2 ±2 LSB typ
T
MIN
to T
MAX
±3 ±12 ±8 LSB max
Bipolar Zero Error at 25°C ±0.5 ±2 ±2 LSB typ
T
MIN
to T
MAX
±4 ±12 ±8 LSB max
Gain Temperature Coefficient
1
±2 ±2 ±2
ppm FSR/
°C typ
Offset Temperature Coefficient
1
±2 ±2 ±2
ppm FSR/
°C typ
Bipolar Zero Temperature
Coefficient1
±2 ±2 ±2
ppm FSR/
°C typ
REFERENCE INPUT
Input Resistance 25 25 25 kΩ min Resistance from V
REF+
to V
REF−
43 43 43 kΩ max Typically 34 kΩ
V
REF+
Range
V
SS
+ 6 to
V
DD
− 6
V
SS
+ 6 to
V
DD
− 6
V
SS
+ 6 to
V
DD
− 6
V
V
REF−
Range
V
SS
+ 6 to
V
DD
− 6
V
SS
+ 6 to
V
DD
− 6
V
SS
+ 6 to
V
DD
− 6
V
OUTPUT CHARACTERISTICS
Output Voltage Swing
V
SS
+ 4 to
V
DD
− 4
V
SS
+ 4 to
V
DD
− 4
V
SS
+ 4 to
V
DD
− 4
V max
Resistive Load 2 2 2 kΩ min To 0 V
Capacitive Load 200 200 200 pF max To 0 V
Output Resistance 0.3 0.3 0.3 Ω typ
Short-Circuit Current ±25 ±25 ±25 mA typ Voltage range: −10 V to +10 V
AD7849
Rev. C | Page 4 of 20
Parameter A Version B Version C Version Unit Test Conditions/Comments
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 2.4 2.4 V min
Input Low Voltage, V
INL
0.8 0.8 0.8 V max
Input Current, I
INH
±10 ±10 ±10 μA max
Input Capacitance, C
IN
10 10 10 pF max
DIGITAL OUTPUTS
Output Low Voltage, V
OL
0.4 0.4 0.4 V max I
SINK
= 1.6 mA
Output High Voltage, V
OH
4.0 4.0 4.0 V min I
SOURCE
= 400 μA
Floating State Leakage Current ±10 ±10 ±10 μA max
Floating State Output
Capacitance
10 10 10 pF max
POWER REQUIREMENTS
2
V
DD
14.25/15.75 14.25/15.75 14.25/15.75 V min/V max
V
SS
−14.25/−15.75 −14.25/−15.75 −14.25/−15.75 V min/V max
V
CC
4.75/5.25 4.75/5.25 4.75/5.25 V min/V max
I
DD
5 5 5 mA max
V
OUT
unloaded, V
INH
= V
DD
– 0.1 V,
V
INL
= 0.1 V
I
SS
5 5 5 mA max
V
OUT
unloaded, V
INH
= V
DD
– 0.1 V,
V
INL
= 0.1 V
I
CC
2.5 2.5 2.5 mA max V
INH
= V
DD
– 0.1 V, V
INL
= 0.1 V
Power Supply Sensitivity
3
0.4 1.5 1.5 LSB/V max
Power Dissipation 100 100 100 mW typ V
OUT
unloaded
1
Guaranteed by design and characterization, not production tested.
2
The AD7849 is functional with power supplies of ±12 V. See the Typical Performance Characteristics section.
3
Sensitivity of gain error, offset error, and bipolar zero error to V
DD
, V
SS
variations.
RESET SPECIFICATIONS
These specifications apply when the device goes into reset mode during power-up or power-down sequence. V
OUT
unloaded.
Table 2.
Parameter All Versions Unit Test Conditions/Comments
V
A
,
1
Low Threshold Voltage for V
DD
, V
SS
1.2 V max This is the lower V
DD
/V
SS
threshold voltage for the reset function.
0 V typ Above this, the reset is activated.
V
B
, High Threshold Voltage for V
DD
, V
SS
9.5 V max This is the higher V
DD
/V
SS
threshold voltage for the reset function.
6.4 V min Below this, the reset is activated. Typically, 8 V.
V
C
, Low Threshold Voltage for V
CC
1 V max This is the lower V
CC
threshold voltage for the reset function.
0 V typ Above this, the reset is activated.
V
D
, High Threshold Voltage for V
CC
4 V max This is the higher V
CC
threshold voltage for the reset function.
2.5 V min Below this, the reset is activated. Typically, 3 V.
G2 R
ON
1 kΩ typ On resistance of G2; V
DD
= 2 V; V
SS
= −2 V; I
G2
= 1 mA.
1
A pull-down resistor (65 kΩ) on V
OUT
maintains 0 V output when V
DD
/V
SS
is below V
A
.
AD7849
Rev. C | Page 5 of 20
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance and are no subject to test. V
REF+
= 5 V; V
DD
= 14.25 V to 15.75 V; V
SS
= −14.25 V to
−15.75 V; V
CC
= 4.75 V to 5.25 V; R
OFS
connected to 0 V.
Table 3.
Parameter A, B, C Versions Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Settling Time
1
7 μs typ To 0.006% FSR. V
OUT
loaded. V
REF−
= 0 V.
10 μs typ To 0.003% FSR. V
OUT
loaded. V
REF−
= −5 V.
Slew Rate 4 V/μs typ
Digital-to-Analog Glitch Impulse 250 nV-sec typ
DAC alternatively loaded with 00 … 00 and
111 … 11. V
OUT
loaded. LDAC permanently low.
BIN
/COMP set to 1. V
REF−
= −5 V.
150 nV-sec typ
LDAC
frequency = 100 kHz.
AC Feedthrough 1 mV p-p typ
V
REF−
= 0 V, V
REF+
= 1 V rms, 10 kHz sine wave.
DAC loaded with all 0s. BIN
/COMP set to 0.
Digital Feedthrough 5 nV-sec typ
DAC alternatively loaded with all 1s and 0s.
SYNC high.
Output Noise Voltage Density, 1 kHz to 100 kHz 80 nV/√Hz typ
Measured at V
OUT
. V
REF+
= V
REF−
= 0 V.
BIN
/COMP set to 0.
1
LDAC
= 0. Settling time does not include deglitching time of 5 μs (typical).
TIMING CHARACTERISTICS
V
DD
= 14.25 V to 15.75 V; V
SS
= −14.25 V to −15.75 V; V
CC
= 4.75 V to 5.25 V; R
L
= 2 kΩ, C
L
= 200 pF. All specifications T
MIN
to T
MAX
,
unless otherwise noted. Guaranteed by characterization. All input signals are specified tr = tf = 5 ns (10% to 90% of 5 V and timed from a
voltage level of 1.6 V.
Table 4.
Parameter Limit at 25°C (All Versions) Limit at T
MIN
, T
MAX
(All Versions) Unit Test Conditions/Comments
t
1
1
200 200 ns min SCLK cycle time
t
2
50 50 ns min
SYNC
-to-SCLK setup time
t
3
70 70 ns min
SYNC
-to-SCLK hold time
t
4
10 10 ns min Data setup time
t
5
40 40 ns min Data hold time
t
6
2
80 80 ns max SCLK falling edge to SDO valid
t
7
80 80 ns min
LDAC
, CLR pulse width
t
r
30 30 μs max Digital input rise time
t
f
30 30 μs max Digital input fall time
1
SCLK mark/space ratio range is 40/60 to 60/40.
2
SDO load capacitance is 50 pF.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7849ARZ

Mfr. #:
Buy AD7849ARZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Serial Input 14B/16B
Lifecycle:
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