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LC87FBH08AU-EB-NH

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
LC87FBH08A
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25
Continued from preceding page.
Parameter Symbol
Pin/
remarks
Conditions
Specification
V
DD
[V] min typ max unit
HALT mode
consumption
current
(Note 10-1)
(Note 10-2)
IDDHALT(7) V
DD
1 HALT mode
FsX’tal=32.768kHz crystal oscillation mode
Internal low speed and medium speed RC
oscillation stopped.
System clock set to 8MHz with
frequency variable RC oscillation
1/1 frequency division ratio
1.8 to 5.5 1.3 2.3
mA
1.8 to 3.6 0.91 1.5
IDDHALT(8) HALT mode
External FsX’tal and FmCF oscillation stopped.
System clock set to internal low speed RC
oscillation.
Internal medium speed RC oscillation stopped.
Frequency variable RC oscillation stopped.
1/1 frequency division ratio
1.8 to 5.5 18 68
A
1.8 to 3.6 11 35
IDDHALT(9) HALT mode
External FsX’tal and FmCF oscillation stopped.
System clock set to internal low speed RC
oscillation.
Internal medium speed RC oscillation stopped.
Frequency variable RC oscillation stopped.
1/1 frequency division ratio
Ta=-10 to +50C
5.0 18 46
3.3 11 27
2.5 7.4 19
IDDHALT(10) HALT mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 32.768kHz side
Internal low speed and medium speed RC
oscillation stopped.
Frequency variable RC oscillation stopped.
1/2 frequency division ratio
1.8 to 5.5 24 98
1.8 to 3.6 8.0 35
IDDHALT(11) HALT mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 32.768kHz side
Internal low speed and medium speed RC
oscillation stopped.
Frequency variable RC oscillation stopped.
1/2 frequency division ratio
Ta=-10 to +50C
5.0 24 63
3.3 8.0 23
2.5 3.5 11
HOLD mode
consumption
current
(Note 10-1)
(Note 10-2)
IDDHOLD(1) HOLD mode
CF1=V
DD
or open (External clock mode)
1.8 to 5.5 0.019 23
1.8 to 3.6 0.011 11
IDDHOLD(2) HOLD mode
CF1=V
DD
or open (External clock mode)
Ta=-10 to +50C
5.0 0.019 1.2
3.3 0.011 0.59
2.5 0.010 0.30
IDDHOLD(3) HOLD mode
CF1=V
DD
or open (External clock mode)
LVD option selected
1.8 to 5.5 2.6 26
1.8 to 3.6 2.0 13
IDDHOLD(4) HOLD mode
CF1=V
DD
or open (External clock mode)
Ta=-10 to +50C
LVD option selected
5.0 2.6 3.8
3.3 2.0 2.8
2.5 1.7 2.5
Timer HOLD
mode
consumption
current
(Note 10-1)
(Note 10-2)
IDDHOLD(5) Timer HOLD mode
FsX’tal=32.768kHz crystal oscillation mode
1.8 to 5.5 22 84
1.8 to 3.6 6.5 30
IDDHOLD(6) Timer HOLD mode
FsX’tal=32.768kHz crystal oscillation mode
Ta=-10 to +50C
5.0 22 53
3.3 6.5 16
2.5 2.7 7.2
Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note10-2: The consumption current values do not include operational current of LVD function if not specified.
LC87FBH08A
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F-ROM Programming Characteristics at Ta = +10C to +55C, V
SS
1 = V
SS
2 = 0V
Parameter Symbol Pin/Remarks Conditions
Specification
V
DD
[V] min typ max unit
Onboard
programming
current
IDDFW(1) V
DD
1 Only current of the Flash block.
2.2 to 5.5 5 10 mA
Programming
time
tFW(1) Erasing time
2.2 to 5.5
20 30 ms
tFW(2) Programming time
40 60 s
UART (Full Duplex) Operating Conditions
at Ta = 40C to +85C, V
SS
1 = V
SS
2 = 0V
Parameter Symbol Pin/Remarks Conditions
Specification
V
DD
[V] min typ max unit
Transfer rate UBR P20, P21
1.8 to 5.5 16/3 8192/3 tCYC
Data length: 7/8/9 bits (LSB first)
Stop bits: 1 bit (2-bit in continuous data transmission)
Parity bits: None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Transmit data (LSB first)
Start of
transmission
End of
transmission
UBR
Start bit
Stop bit
UBR
Receive data (LSB first)
Start of
reception
End of
reception
Start bit
Stop bit
LC87FBH08A
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27
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
CF oscillation normal amplifier size selected (CFLAMP=0)
MURATA
Nominal
Frequency
Type Oscillator Name
Circuit Constant
Operating
Voltage
Range
[V]
Oscillation
Stabilization Time
Remarks
C1
[pF]
C2
[pF]
Rf
[]
Rd
[]
typ
[ms]
max
[ms]
12MHz SMD CSTCE12M0G52-R0 (10) (10) Open 680 2.6 to 5.5 0.02 0.3
Internal
C1, C2
10MHz
SMD CSTCE10M0G52-R0 (10) (10) Open 680 2.1 to 5.5 0.02 0.3
LEAD
CSTLS10M0G53-B0 (15) (15) Open 680 2.4 to 5.5 0.02 0.3
CSTLS10M0G53095-B0 (15) (15) Open 680 2.0 to 5.5 0.01 0.15
8MHz
SMD CSTCE8M00G52-R0 (10) (10) Open 1k 2.1 to 5.5 0.02 0.3
LEAD
CSTLS8M00G53-B0 (15) (15) Open 1k 2.2 to 5.5 0.02 0.3
CSTLS8M00G53095-B0 (15) (15) Open 1k 1.9 to 5.5 0.01 0.15
6MHz
SMD
CSTCR6M00G53-R0 (15) (15) Open 1.5k 2.0 to 5.5 0.02 0.3
CSTCR6M00G53093-R0 (15) (15) Open 1.5k 1.8 to 5.5 0.01 0.15
LEAD
CSTLS6M00G53-B0 (15) (15) Open 1.5k 2.0 to 5.5 0.02 0.3
CSTLS6M00G53095-B0 (15) (15) Open 1.5k 1.8 to 5.5 0.01 0.15
4MHz
SMD CSTCR4M00G53-R0 (15) (15) Open 1.5k 1.8 to 5.5 0.03 0.45
LEAD CSTLS4M00G53-B0 (15) (15) Open 1.5k 1.8 to 5.5 0.02 0.3
CF oscillation low amplifier size selected (CFLAMP=1)
MURATA
Nominal
Frequency
Type Oscillator Name
Circuit Constant
Operating
Voltage
Range
[V]
Oscillation
Stabilization Time
Remarks
C1
[pF]
C2
[pF]
Rf
[]
Rd
[]
typ
[ms]
max
[ms]
12MHz SMD CSTCE12M0G52-R0 (10) (10) Open 470 3.9 to 5.5 0.03 0.45
Internal
C1, C2
10MHz
SMD CSTCE10M0G52-R0 (10) (10) Open 470 2.9 to 5.5 0.03 0.45
LEAD
CSTLS10M0G53-B0 (15) (15) Open 470 3.6 to 5.5 0.03 0.45
CSTLS10M0G53095-B0 (15) (15) Open 470 2.7 to 5.5 0.02 0.3
8MHz
SMD CSTCE8M00G52-R0 (10) (10) Open 680 2.7 to 5.5 0.03 0.45
LEAD
CSTLS8M00G53-B0 (15) (15) Open 680 3.0 to 5.5 0.03 0.45
CSTLS8M00G53095-B0 (15) (15) Open 680 2.5 to 5.5 0.01 0.15
6MHz
SMD
CSTCR6M00G53-R0 (15) (15) Open 1k 2.6 to 5.5 0.03 0.45
CSTCR6M00G53095-R0 (15) (15) Open 1k 2.2 to 5.5 0.02 0.3
LEAD
CSTLS6M00G53-B0 (15) (15) Open 1k 2.7 to 5.5 0.03 0.45
CSTLS6M00G53095-B0 (15) (15) Open 1k 2.2 to 5.5 0.01 0.15
4MHz
SMD
CSTCR4M00G53-R0 (15) (15) Open 1k 2.1 to 5.5 0.04 0.6
CSTCR4M00G53095-R0 (15) (15) Open 1k 1.8 to 5.5 0.02 0.3
LEAD
CSTLS4M00G53-B0 (15) (15) Open 1k 2.1 to 5.5 0.02 0.3
CSTLS4M00G53095-B0 (15) (15) Open 1k 1.8 to 5.5 0.01 0.15
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in
follwing cases (see Figure 3).
The time interval that is required for the oscillation to get stabilized after the instruction for starting the mainclock
oscillation circuit is executed.
The time interval that is required for the oscillation to get stabilized after the HOLD mode is reset and oscillation is
started.
The time interval that is required for the oscillation to get stabilized after the X’tal Hold mode, under the state which
the main clock oscillation is enabled, is reset and oscillation is started.
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LC87FBH08AU-EB-NH

Mfr. #:
Buy LC87FBH08AU-EB-NH
Manufacturer:
ON Semiconductor
Description:
8-bit Microcontrollers - MCU 8-BIT MICROCONTROLLER
Lifecycle:
New from this manufacturer.
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