REV. D
ADSP-2181
–16–
Parameter Min Max Unit
Bus Request/Grant
Timing Requirements:
t
BH
BR Hold after CLKOUT High
1
0.25t
CK
+ 2 ns
t
BS
BR Setup before CLKOUT Low
1
0.25t
CK
+ 17 ns
Switching Characteristics:
t
SD
CLKOUT High to xMS, 0.25t
CK
+ 10 ns
RD, WR Disable
t
SDB
xMS, RD, WR
Disable to BG Low 0 ns
t
SE
BG High to xMS,
RD, WR Enable 0 ns
t
SEC
xMS, RD, WR
Enable to CLKOUT High 0.25t
CK
– 4 ns
t
SDBH
xMS, RD, WR
Disable to BGH Low
2
0ns
t
SEH
BGH High to xMS,
RD, WR Enable
2
0ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
SDBH
t
SEH
t
BS
BR
t
BH
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
Figure 10. Bus Request–Bus Grant
ADSP-2181
–17–
REV. D
Parameter Min Max Unit
Memory Read
Timing Requirements:
t
RDD
RD Low to Data Valid 0.5t
CK
– 9 + w ns
t
AA
A0–A13, xMS to Data Valid 0.75t
CK
– 10.5 + w ns
t
RDH
Data Hold from RD High 0 ns
Switching Characteristics:
t
RP
RD Pulsewidth 0.5t
CK
– 5 + w ns
t
CRD
CLKOUT High to RD Low 0.25t
CK
– 5 0.25t
CK
+ 7 ns
t
ASR
A0–A13, xMS Setup before RD Low 0.25t
CK
– 4 ns
t
RDA
A0–A13, xMS Hold after RD Deasserted 0.25t
CK
– 3 ns
t
RWR
RD High to RD or WR Low 0.5t
CK
– 5 ns
w = wait states × t
CK
.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
D
t
RDA
t
RWR
t
RP
t
ASR
t
CRD
t
RDD
t
AA
t
RDH
DMS, PMS,
BMS, IOMS,
CMS
RD
WR
Figure 11. Memory Read
REV. D
ADSP-2181
–18–
Parameter Min Max Unit
Memory Write
Switching Characteristics:
t
DW
Data Setup before WR High 0.5t
CK
– 7 + w ns
t
DH
Data Hold after WR High 0.25t
CK
– 2 ns
t
WP
WR Pulsewidth 0.5t
CK
– 5 + w ns
t
WDE
WR Low to Data Enabled 0 ns
t
ASW
A0–A13, xMS Setup before WR Low 0.25t
CK
– 4 ns
t
DDR
Data Disable before WR or RD Low 0.25t
CK
– 4 ns
t
CWR
CLKOUT High to WR Low 0.25t
CK
– 5 0.25 t
CK
+ 7 ns
t
AW
A0–A13, xMS, Setup before WR Deasserted 0.75t
CK
– 9 + w ns
t
WRA
A0–A13, xMS Hold after WR Deasserted 0.25t
CK
– 3 ns
t
WWR
WR High to RD or WR Low 0.5t
CK
– 5 ns
w = wait states × t
CK
.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
D
t
WP
t
AW
t
CWR
t
DH
t
WDE
t
DW
t
ASW
t
WWR
t
WRA
t
DDR
DMS, PMS,
BMS, CMS,
IOMS
RD
WR
Figure 12. Memory Write

ADSP-2181KSZ-160

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16B 40 MIPS 5V 2 Serial Prts Host Prt
Lifecycle:
New from this manufacturer.
Delivery:
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