REV. D
ADSP-2181
–22–
Parameter Min Max Unit
IDMA Write, Long Write Cycle
Timing Requirements:
t
IKW
IACK Low before Start of Write
1
0ns
t
IKSU
IAD15–0 Data Setup before IACK Low
2, 3
0.5t
CK
+ 10 ns
t
IKH
IAD15–0 Data Hold after IACK Low
2, 3
2ns
Switching Characteristics:
t
IKLW
Start of Write to IACK Low
4
1.5t
CK
ns
t
IKHW
Start of Write to IACK High 15 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications t
IDSU
, t
IDH
.
3
If Write Pulse ends after IACK Low, use specifications t
IKSU
, t
IKH
.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the User’s Manual.
IAD15–0
DATA
t
IKHW
t
IKW
IACK
IS
IWR
t
IKLW
t
IKH
t
IKSU
Figure 16. IDMA Write, Long Write Cycle
ADSP-2181
–23–
REV. D
Parameter Min Max Unit
IDMA Read, Long Read Cycle
Timing Requirements:
t
IKR
IACK Low before Start of Read
1
0ns
t
IRP
Duration of Read 15 ns
Switching Characteristics:
t
IKHR
IACK High after Start of Read
1
15 ns
t
IKDS
IAD15–0 Data Setup before IACK Low 0.5t
CK
– 10 ns
t
IKDH
IAD15–0 Data Hold after End of Read
2
0ns
t
IKDD
IAD15–0 Data Disabled after End of Read
2
12 ns
t
IRDE
IAD15–0 Previous Data Enabled after Start of Read 0 ns
t
IRDV
IAD15–0 Previous Data Valid after Start of Read 15 ns
t
IRDH1
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)
3
2t
CK
– 5 ns
t
IRDH2
IAD15–0 Previous Data Hold after Start of Read (PM2)
4
t
CK
– 5 ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
t
IRP
t
IKR
PREVIOUS
DATA
READ
DATA
t
IKHR
t
IKDS
t
IRDV
t
IRDH
t
IKDD
t
IRDE
t
IKDH
IAD15–0
IACK
IS
IRD
Figure 17. IDMA Read, Long Read Cycle
REV. D
ADSP-2181
–24–
Parameter Min Max Unit
IDMA Read, Short Read Cycle
Timing Requirements:
t
IKR
IACK Low before Start of Read
1
0ns
t
IRP
Duration of Read 15 ns
Switching Characteristics:
t
IKHR
IACK High after Start of Read
1
15 ns
t
IKDH
IAD15–0 Data Hold after End of Read
2
0ns
t
IKDD
IAD15–0 Data Disabled after End of Read
2
12 ns
t
IRDE
IAD15–0 Previous Data Enabled after Start of Read 0 ns
t
IRDV
IAD15–0 Previous Data Valid after Start of Read 15 ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
t
IRP
t
IKR
PREVIOUS
DATA
t
IKHR
t
IRDV
t
IKDD
t
IRDE
t
IKDH
IAD15–0
IACK
IS
IRD
Figure 18. IDMA Read, Short Read Cycle

ADSP-2181KSZ-160

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16B 40 MIPS 5V 2 Serial Prts Host Prt
Lifecycle:
New from this manufacturer.
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