ADSP-2181
–25–
REV. D
OUTPUT DRIVE CURRENTS
Figure 19 shows typical I-V characteristics for the output drivers
of the ADSP-2181. The curves represent the current drive
capability of the output drivers as a function of output voltage.
SOURCE VOLTAGE – Volts
SOURCE CURRENT – mA
120
–80
01 6
2345
100
0
–20
–40
–60
80
60
20
40
5.5V, –408C
5.0V, +258C
4.5V, +858C
4.5V, +858C
5.0V, +258C
5.5V, –408C
Figure 19. Typical Drive Currents
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × V
DD
2
× f
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
External data memory is accessed every cycle with 50% of the
address pins switching.
External data memory writes occur every other cycle with
50% of the data pins switching.
Each address and data pin has a 10 pF total load at the pin.
The application operates at V
DD
= 5.0 V and t
CK
= 30 ns.
Total Power Dissipation = P
INT
+ (C × V
DD
2
× f )
P
INT
= internal power dissipation from Power vs. Frequency
graph (Figure 20).
TEMPERATURE – °C
1000
1
100
10
CURRENT (LOG SCALE) – mA
58515 25 35 45 55 65 75
–5
V
DD
= 5.5V
V
DD
= 5.0V
V
DD
= 4.5V
NOTES:
1. REFLECTS ADSP-2181 OPERATION IN LOWEST POWER MODE.
(SEE “SYSTEM INTERFACE" CHAPTER OF THE
ADSP-2100 FAMILY
USER'S MANUAL, THIRD EDITION,
FOR DETAILS.)
2. CURRENT REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
Figure 20. Power-Down Supply Current (Typical)
(C × V
DD
2
× f ) is calculated for each output:
# of
Pins × C × V
DD
2
× f
Address, DMS 8 × 10 pF × 5
2
V × 33.3 MHz = 66.6 mW
Data Output, WR 9 × 10 pF × 5
2
V × 16.67 MHz = 37.5 mW
RD 1 × 10 pF × 5
2
V × 16.67 MHz = 4.2 mW
CLKOUT 1 × 10 pF × 5
2
V × 33.3 MHz = 8.3 mW
116.6 mW
Total power dissipation for this example is P
INT
+ 116.6 mW.
1/t
CK
– MHz
POWER (P
INT
) – mW
220
30 32 42
34 36 38 40
420
370
320
270
570
470
520
2181 POWER, INTERNAL
1, 3, 4
V
DD
= 5.5V
V
DD
= 5.0V
V
DD
= 4.5V
410mW
325mW
250mW
550mW
425mW
330mW
28
POWER (P
IDLE
) – mW
1/t
CK
– MHz
100
40
30 32 4234 36 38 40
70
60
50
90
80
30
POWER, IDLE
1, 2, 3
V
DD
= 5.5V
V
DD
= 5.0V
V
DD
= 4.5V
77mW
60mW
45mW
95mW
75mW
54mW
28
1/t
CK
– MHz
POWER (P
IDLE
n
) – mW
80
30
30 32 42
34 36 38 40
75
50
45
40
35
70
65
55
60
POWER, IDLE
n
MODES
3
IDLE
IDLE (16)
IDLE (128)
60mW
35mW
34mW
39mW
37mW
75mW
28
VALID FOR ALL TEMPERATURE GRADES.
4
I
DD
MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14),
30% ARE TYPE 2 AND TYPE 6 AND 20% ARE IDLE INSTRUCTIONS.
3
TYPICAL POWER DISSIPATION AT 5.0V V
DD
AND 258C EXCEPT WHERE SPECIFIED.
2
IDLE REFERS TO ADSP-2181 STATE OF OPERATION DURING EXECUTION OF IDLE
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V
DD
OR GND.
Figure 21. Power vs. Frequency
REV. D
ADSP-2181
–26–
CAPACITIVE LOADING
Figures 22 and 23 show the capacitive loading characteristics of
the ADSP-2181.
C
L
– pF
RISE TIME (0.4V–2.4V) – ns
0
50
100 150 200 250
25
15
10
5
0
20
Figure 22. Range of Output Rise Time vs. Load Capaci-
tance, C
L
(at Maximum Ambient Operating Temperature)
C
L
– pF
14
0
VALID OUTPUT DELAY OR HOLD – ns
50 100 150 250200
12
4
2
–2
10
8
16
6
–4
0
Figure 23. Range of Output Valid Delay or Hold vs. Load
Capacitance, C
L
(at Maximum Ambient Operating
Temperature)
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (t
DIS
) is the difference of t
MEASURED
and t
DECAY
,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low volt-
age level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
t
DECAY
, is dependent on the capacitive load, C
L
, and the current
load, i
L
, on the output pin. It can be approximated by the fol-
lowing equation:
t
DECAY
=
C
L
×0.5V
i
L
from which
t
DIS
= t
MEASURED
t
DECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
1.5V
INPUT
OR
OUTPUT
1.5V
Figure 24. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t
ENA
) is the interval from when
a reference signal reaches a high or low voltage level to when
the output has reached a specified high or low trip point, as
shown in the Output Enable/Disable diagram. If multiple pins
(such as the data bus) are enabled, the measurement value is
that of the first pin to start driving.
2.0V
1.0V
t
ENA
REFERENCE
SIGNAL
OUTPUT
t
DECAY
V
OH
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
t
DIS
t
MEASURED
V
OL
(MEASURED)
V
OH
(MEASURED) – 0.5V
V
OL
(MEASURED) +0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
V
OH
(MEASURED)
V
OL
(MEASURED)
Figure 25. Output Enable/Disable
TO
OUTPUT
PIN
50pF
+1.5V
I
OH
I
OL
Figure 26. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
ADSP-2181
–27–
REV. D
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
T
AMB
=T
CASE
– (PD × θ
CA
)
T
CASE
= Case Temperature in °C
PD = Power Dissipation in W
θ
CA
= Thermal Resistance (Case-to-Ambient)
θ
JA
= Thermal Resistance (Junction-to-Ambient)
θ
JC
= Thermal Resistance (Junction-to-Case)
Package θ
JA
θ
JC
θ
CA
TQFP 50°C/W 2°C/W 48°C/W
PQFP 41°C/W 10°C/W 31°C/W

ADSP-2181KSZ-160

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16B 40 MIPS 5V 2 Serial Prts Host Prt
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