ADSP-2181
–19–
REV. D
Parameter Min Max Unit
Serial Ports
Timing Requirements:
t
SCK
SCLK Period 50 ns
t
SCS
DR/TFS/RFS Setup before SCLK Low 4 ns
t
SCH
DR/TFS/RFS Hold after SCLK Low 7 ns
t
SCP
SCLK
IN
Width 20 ns
Switching Characteristics:
t
CC
CLKOUT High to SCLK
OUT
0.25t
CK
0.25t
CK
+ 10 ns
t
SCDE
SCLK High to DT Enable 0 ns
t
SCDV
SCLK High to DT Valid 15 ns
t
RH
TFS/RFS
OUT
Hold after SCLK High 0 ns
t
RD
TFS/RFS
OUT
Delay from SCLK High 15 ns
t
SCDH
DT Hold after SCLK High 0 ns
t
TDE
TFS (Alt) to DT Enable 0 ns
t
TDV
TFS (Alt) to DT Valid 14 ns
t
SCDD
SCLK High to DT Disable 15 ns
t
RDV
RFS
(Multichannel, Frame Delay Zero) to DT Valid 15 ns
CLKOUT
SCLK
TFS
OUT
RFS
OUT
DT
ALTERNATE
FRAME MODE
t
CC
t
CC
t
SCS
t
SCH
t
RH
t
SCDE
t
SCDH
t
SCDD
t
TDE
t
RDV
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
DR
TFS
IN
RFS
IN
RFS
OUT
TFS
OUT
t
TDV
t
SCDV
t
RD
t
SCP
t
SCK
t
SCP
TFS
IN
RFS
IN
ALTERNATE
FRAME MODE
t
RDV
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
t
TDV
t
TDE
Figure 13. Serial Ports
REV. D
ADSP-2181
–20–
Parameter Min Max Unit
IDMA Address Latch
Timing Requirements:
t
IALP
Duration of Address Latch
1, 2
10 ns
t
IASU
IAD15–0 Address Setup before Address Latch End
2
5ns
t
IAH
IAD15–0 Address Hold after Address Latch End
2
2ns
t
IKA
IACK Low before Start of Address Latch
1
0ns
t
IALS
Start of Write or Read after Address Latch End
2, 3
3ns
NOTES
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
t
IKA
IAD15–0
IACK
IAL
IS
IRD
IWR
OR
t
IALP
t
IASU
t
IAH
t
IALS
Figure 14. IDMA Address Latch
ADSP-2181
–21–
REV. D
Parameter Min Max Unit
IDMA Write, Short Write Cycle
Timing Requirements:
t
IKW
IACK Low before Start of Write
1
0ns
t
IWP
Duration of Write
1, 2
15 ns
t
IDSU
IAD15–0 Data Setup before End of Write
2, 3, 4
5ns
t
IDH
IAD15–0 Data Hold after End of Write
2, 3, 4
2ns
Switching Characteristic:
t
IKHW
Start of Write to IACK High 15 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications t
IDSU
, t
IDH
.
4
If Write Pulse ends after IACK Low, use specifications t
IKSU
, t
IKH
.
IAD15–0
DATA
t
IKHW
t
IKW
t
IDSU
IACK
t
IWP
t
IDH
IS
IWR
Figure 15. IDMA Write, Short Write Cycle

ADSP-2181KSZ-160

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16B 40 MIPS 5V 2 Serial Prts Host Prt
Lifecycle:
New from this manufacturer.
Delivery:
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