IDT5T9890NLGI Datasheet IDT5T9890NLI, IDT5T9890NLGI, IDT5T9890NLGI8 | P28-P30

INDUSTRIAL TEMPERATURE RANGE

IDT5T9890

EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER

EEPROM OPERATION

(see I

C Interface Definition for the EEPROM instructions)

The IDT5T9890 can also store its configuration in internal EEPROM. The contents of the device’s internal programming registers can be saved to the EEPROM

by issuing a save instruction (ProgSave) and can be loaded back to the internal programming registers by issuing a restore instruction (ProgRestore). To

initiate a save or restore, only two bytes are transferred. The Device Address is issued with the read/write bit set to ‘0’ followed by the appropriate Command

Code. The save or restore instruction executes after the STOP condition is received, during which time the IDT5T9890 will not generate Acknowledge bits.

The device is ready to accept a new programming instruction once it Acknowledges its 7-bit address. The time it takes for the save and restore instructions

to complete depends on the PLL oscillator frequency, FVCO. The restore time, TRESTORE, and the save time, TSAVE, can be calculated as follows:

TRESTORE

= 1.23X10

/FVCO

(mS)

TSAVE

= 3.09X10

FVCO

+ 52 (mS)

In order for the save and restore instructions to function properly, the IDT5T9890 must not be in power-down mode (PD must be HIGH), and the PLL must

be enabled (PLL_EN must be LOW and Bit 57 = 0).

On power-up of the IDT5T9890, an automatic restore is performed to load the EEPROM contents into the internal programming registers. The auto-restore

will not function properly if the device is in power-down mode (PD must be HIGH). The device’s auto-restore feature will function regardless of the state of

the PLL_EN pin or Bit 57. The IDT5T9890 will be ready to accept a programming instruction once it acknowledges its 7-bit I

C address. The time it takes

for the device to complete the auto-restore is approximately 3ms.

PROGRAMMING NOTES

Once the IDT5T9890 has been programmed either with a ProgWrite or ProgRestore instruction, the device will attempt to achieve phase lock using the new

PLL configuration. If there is a valid REF and FB input clock connected to the device and it does not achieve lock, the user should issue a ProgRead instruction

to confirm that the PLL configuration data is valid.

On power-up and before the automatic ProgRestore instruction has completed, the internal programming registers will contain the value of ‘0’ for all bits 95:0.

The PLL will remain at the minimum frequency and will not achieve phase lock until after the automatic restore is completed. If the outputs are enabled by the

nSOE pins, the outputs will toggle at the minimum frequency. If the outputs are disabled by the nSOE pins and the OMODE pin is set HIGH, the nQ[1:0] and

QFB are stopped HIGH, while QFB is stopped LOW.

SCLK

SDA

tSU:START tSU:STOP

STOP

Data can

change

Address or data

valid

HD:START

START

SCLK

SDA IN

tSU:START tSU:STOP

tHD:START

tLOW

tHIGH

tHD:DATA

tSU:DATA

tBUF

tR tF

tOVDtOVD

SDA OUT

Figure 1: I

C Timing Data

INDUSTRIAL TEMPERATURE RANGE

IDT5T9890

EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER

C INTERFACE DEFINITION

ProgWrite S

Device Address Command Code

7'b1101xxx 0 8'bxxxxxx00AA

Data

Data Byte 1 (Bits 95 - 88)

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12 (Bits 7 - 0)

A . . .

A P

Device Address

7'b1101xxx 1

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12 (Bits 7 - 0)

A . . .

A P

ID Byte

Data Byte 1 (Bits 95 - 88)

Data Byte 2

Data Byte 3

A . . .Reserved Byte

A . . .8'b00000110

ProgRead

ProgSave S

Device Address Command Code

7'b1101xxx 0 8'bxxxxxx01

A A P

ProgRestore S

Device Address Command Code

7'b1101xxx 0 8'bxxxxxx10

A A P

ID Byte:

Part # ID

5T9890 00000110

INDUSTRIAL TEMPERATURE RANGE

IDT5T9890

EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER

C BUS DC CHARACTERISTICS

Symbol Parameter Conditions Min Typ Max Unit

VIH Input HIGH Level 0.7 * VDD V

VIL Input LOW Level 0.3 * VDD V

VHYS Hysteresis of Inputs 0.05 * VDD V

IIN Input Leakage Current ±1.0 µA

OL Output LOW Voltage IOL = 3 mA 0.4 V

C BUS AC CHARACTERISTICS FOR STANDARD MODE

Symbol Parameter Min Typ Max Unit

FSCLK Serial Clock Frequency (SCLK) 0 100 KHz

tBUF Bus free time between STOP and START 4.7 µs

tSU:START Setup Time, START 4.7 µs

tHD:START Hold Time, START 4 µs

tSU:DATA Setup Time, data input (SDA) 250 ns

tHD:DATA Hold Time, data input (SDA)

(1)

0 µs

tOVD Output data valid from clock 3.45 µs

CB Capacitive Load for Each Bus Line 400 pF

tR Rise Time, data and clock (SDA, SCLK) 1000 ns

tF Fall Time, data and clock (SDA, SCLK) 300 ns

tHIGH HIGH Time, clock (SCLK) 4 µs

tLOW LOW Time, clock (SCLK) 4.7 µs

SU:STOP Setup Time, STOP 4 µs

C BUS AC CHARACTERISTICS FOR FAST MODE

Symbol Parameter Min Typ Max Unit

FSCLK Serial Clock Frequency (SCLK) 0 400 KHz

tBUF Bus free time between STOP and START 1.3 µs

tSU:START Setup Time, START 0.6 µs

tHD:START Hold Time, START 0.6 µs

tSU:DATA Setup Time, data input (SDA) 100 ns

tHD:DATA Hold Time, data input (SDA)

(1)

0 µs

tOVD Output data valid from clock 0.9 µs

CB Capacitive Load for Each Bus Line 400 pF

tR Rise Time, data and clock (SDA, SCLK) 20 + 0.1 * CB 300 ns

tF Fall Time, data and clock (SDA, SCLK) 20 + 0.1 * CB 300 ns

tHIGH HIGH Time, clock (SCLK) 0.6 µs

tLOW LOW Time, clock (SCLK) 1.3 µs

SU:STOP Setup Time, STOP 0.6 µs

NOTE:

1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge of

SCLK.

NOTE:

1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge of

SCLK.

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IDT5T9890NLGI

Mfr. #:

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IC CLK DRIVER 2.5V PLL 68-VFQFPN

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