33
INDUSTRIAL TEMPERATURE RANGE
IDT5T9890
EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER
THE INSTRUCTION REGISTER
The Instruction register allows an instruction to be shifted in serially into the
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is
latched at the completion of the shifting process when the TAP controller is at
Update- IR state.
The instruction register must contain 4 bit instruction register-based cells
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in serial
31 (MSB) 28 27 12 11 1 0(LSB)
Version (4 bits) Part number Manufacturer ID 1
0X0 (16-bit) (11-bit) 0X33
path. When the bypass register is selected by an instruction, the shift register
stage is set to a logic zero on the rising edge of TCLK when the TAP controller
is in the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
THE BOUNDARY-SCAN REGISTER
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is
dropped in the 11-bit Manufacturer ID field.
For the IDT5T9890, the Part Number field is 0x3A8.
JTAG INSTRUCTION REGISTER
The Instruction register allows instruction to be serially input into the device
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
• Select test data registers that may operate while the instruction is current.
The other test data registers should not interfere with chip operation and the
selected data register.
IR (3) IR (2) IR (1) IR (0) Instruction Function
0 0 0 0 EXTEST Select boundary scan register
0 0 0 1 SAMPLE/PRELOAD Select boundary scan register
0 0 1 0 IDCODE Select chip identification data register
0 0 1 1 Reserved
0 1 0 0 PROGWRITE Writing to the volatile programming registers
0 1 0 1 PROGREAD Reading from the volatile programming registers
0 1 1 0 PROGSAVE Saving the contents of the volatile programming registers to the EEPROM
0 1 1 1 PROGRESTORE Loading the EEPROM contents into the volatile programming registers
1 0 0 0 CLAMP JTAG
1 0 0 1 HIGHZ JTAG
1 0 1 X BYPASS Select bypass register
1 1 X X BYPASS Select bypass register
JTAG INSTRUCTION REGISTER DECODING
• Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4-bit field (i.e.IR3, IR2, IR1, IR0) to decode
sixteen different possible instructions. Instructions are decoded as follows.
JTAG DEVICE IDENTIFICATION
REGISTER
