34
INDUSTRIAL TEMPERATURE RANGE
IDT5T9890
EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER
The following sections provide a brief description of each instruction. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the IC into an external boundary-
test mode and selects the boundary-scan register to be connected between
TDI and TDO. During this instruction, the boundary-scan register is accessed
to drive test data off-chip through the boundary outputs, and recieve test data
off-chip through the boundary inputs. As such, the EXTEST instruction is the
workhorse of IEEE. Std 1149.1, providing for probe-less testing of solder-joint
opens/shorts and of logic cluster function.
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
normal functional mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a data scan operation, to take a sample of the functional data
entering and leaving the IC.
IDCODE
The optional IDCODE instruction allows the IC to remain in its functional mode
and selects the optional device identification register to be connected between
TDI and TDO. The device identification register is a 32-bit shift register
containing information regarding the IC manufacturer, device type, and
version code. Accessing the device identification register does not interfere
with the operation of the IC. Also, access to the device identification register
should be immediately available, via a TAP data-scan operation, after power-
up of the IC or after the TAP has been reset using the optional TRST pin or
by otherwise moving to the Test-Logic-Reset state.
PROGWRITE
The PROGWRITE instruction is for writing the IDT5T9890 configuration
data to the device’s volatile programming registers. This instruction selects the
programming register path for shifting data from TDI to TDO during data register
scanning. The programming register path has 112 registers (14 bytes)
between TDI and TDO. The 12 configuration data bytes are scanned in
through TDI first, starting with Bit 0. After scanning in the last configuration bit,
Bit 95, sixteen additional bits must be scanned in to place the configuration data
in the proper location. The last sixteen registers in the programming path are
reserved, read-only registers.
PROGREAD
The PROGREAD instruction is for reading out the IDT5T9890 configuration
data from the device’s volatile programming registers. This instruction selects
the programming register path for shifting data from TDI to TDO during data
register scanning. The programming register path has 112 registers between
TDI and TDO, and the first bit scanned out through TDO will be Bit 0 of the
configuration data.
PROGSAVE and PROGRESTORE (EEPROM OPERATION)
The PROGSAVE instruction is for copying the IDT5T9890 configuration
data from the device’s volatile programming registers to the EEPROM. This
instruction selects the BYPASS register path for shifting data from TDI to TDO
during data register scanning.
The PROGRESTORE instruction is for loading the IDT5T9890 configuration
data from the EEPROM to the device’s volatile programming registers. This
instruction selects the BYPASS register path for shifting data from TDI to TDO
during data register scanning.
During the execution of a PROGSAVE or PROGRESTORE instruction, the
IDT5T9890 will not accept a new programming instruction (read, write, save,
or restore). All non-programming JTAG instructions will function properly, but
the user should wait until the save or restore is complete before issuing a new
programming instruction. The time it takes for the save and restore instructions
to complete depends on the PLL oscillator frequency, FVCO. The restore time,
TRESTORE, and the save time, TSAVE, can be calculated as follows:
TRESTORE
= 1.23X10
9
/FVCO
(mS)
TSAVE
= 3.09X10
9
/
FVCO
+ 52 (mS)
If a new programming instruction is issued before the save or restore
completes, the new instruction is ignored, and the BYPASS register path
remains in effect for shifting data from TDI to TDO during data register scanning.
In order for the ProgSave and ProgRestore instructions to function properly,
the IDT5T9890 must not be in power-down mode (PD must be HIGH), and
the PLL must be enabled (PLL_EN = LOW and Bit 57 = 0).
On power-up of the IDT5T9890, an automatic restore is performed to load
the EEPROM contents into the internal programming registers. The auto-
restore will not function properly if the device is in power-down mode (PD must
be HIGH). The device's auto-restore feature will function regardless of the state
of the PLL_EN pin or Bit 57. The time it takes for the device to complete the
auto-restore is approximately 3ms.
CLAMP
The optional CLAMP instruction loads the contents from the boundary-scan
register onto the outputs of the IC, and selects the one-bit bypass register to
be connected between TDI and TDO. During this instruction, data can be
shifted through the bypass register from TDI to TDO without affecting the
condition of the IC outputs.
HIGH-IMPEDANCE
The optional High-Impedance instruction sets all outputs (including two-state
as well as three-state types) of an IC to a disabled (high-impedance) state and
selects the one-bit bypass register to be connected between TDI and TDO.
During this instruction, data can be shifted through the bypass register from TDI
to TDO without affecting the condition of the IC outputs.
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferred through the IC from TDI to TDO without affecting the operation of
the IC.
35
INDUSTRIAL TEMPERATURE RANGE
IDT5T9890
EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER
JTAG
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter Min. Max. Units
tTCLK JTAG Clock Input Period 100 ns
tTCLKHIGH JTAG Clock HIGH 40 ns
tTCLKLOW JTAG Clock Low 40 ns
tTCLKRISE JTAG Clock Rise Time 5
(1)
ns
tTCLKFALL JTAG Clock Fall Time 5
(1)
ns
tRST JTAG Reset 50 ns
tRSR JTAG Reset Recovery 50 ns
NOTE:
1. Guaranteed by design.
Standard JTAG Timing
NOTE:
t1 = tTCLKLOW
t2 = tTCLKHIGH
t3 = tTCLKFALL
t4 = tTCLKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
TCLK
TDI/TMS
TDO
TRST
t
TCLK
t1
t2
t3
t4
t5
t6
t
DS tDH
tDO
TDO
SYSTEM INTERFACE PARAMETERS
Symbol Parameter Min. Max. Units
tDO Data Output
(1)
—20ns
tDOH Data Output Hold
(1)
0—ns
tDS Data Input, tRISE = 3ns 10 ns
tDH Data Input, tFALL = 3ns 10 ns
NOTE:
1. 50pF loading on external output signals.
PROGRAMMING NOTES
Once the IDT5T9890 has been programmed either with a ProgWrite or ProgRestore instruction, the device will attempt to achieve phase lock using the new
PLL configuration. If there is a valif REF and FB input clock connected to the device, and it does not achieve lock, the user should issue a ProgRead instruction
to confirm that the PLL configuration data is valid.
On power-up and before the automatic ProgRestore instruction has completed, the internal programming registers will contain the value of '0' for all bits 95:0.
The PLL will remain at the minimum frequency and will not achieve phase lock until after the automatic restore is completed. If the outputs are enabled by the
nSOE pins, the outputs will toggle at the minimum frequency. If the outputs are disabled by the nSOE pins, and the OMODE pin is set high, the nQ[1:0] and
QFB are stopped HIGH, while QFB is stopped LOW.
36
INDUSTRIAL TEMPERATURE RANGE
IDT5T9890
EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER
RECOMMENDED LANDING PATTERN
NL 68 pin
NOTE: All dimensions are in millimeters.

IDT5T9890NLGI

Mfr. #:
Manufacturer:
Description:
IC CLK DRIVER 2.5V PLL 68-VFQFPN
Lifecycle:
New from this manufacturer.
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