Data Sheet SSM2604
Rev. A | Page 15 of 28
SOFTWARE CONTROL INTERFACE
The software control interface provides access to the user-
selectable control registers and can operate with a 2-wire (I
2
C®)
interface.
Within each control register is a control data-word consisting
of 16 bits, MSB first. Bit D15 to Bit D9 are the register map
address, and Bit D8 to Bit D0 are register data for the associated
register map.
SDIN generates the serial control data-word; SCLK clocks the
serial data,
The device address for the SSM2604 is 0011010.
CONTROL REGISTER SEQUENCING
1. Enable all of the necessary power management bits of
Register R6 with the exception of the out bit (Bit D4). The
out bit should be set to 1 until the final step of the control
register sequence.
2. After the power management bits are set, program all other
necessary registers, with the exception of the active bit
[Register R9, Bit D0] and the out bit of the power
management register.
3. As described in the Digital Core section of the Theory of
Operation, insert enough delay time to charge the VMID
decoupling capacitor before setting the active bit [Register
R9, Bit D0].
4. Finally, to enable the DAC output path of the SSM2603, set
the out bit of Register R6 to 0.
P
98
1 TO 7
98
1 TO 7
98
1 TO 7
S
SDIN
SCL
START ADDR R/W ACK ACKSUBADDRESS ACK STOPDATA
06978-019
Figure 24. 2-Wire I
2
C Generalized Clocking Diagram
WRITE
SEQUENCE
READ
SEQUENCE
SA1A7 A0 A(S) A(S) SD15 D9 0
01
0P
0... A1A7 A0 A(S)... D0 D8D7 A(M) A(M)...
D0D7 P...
......
DEVICE
ADDRESS
DEVICE
ADDRESS
REGISTER
ADDRESS
SA1A7 A0 A(S) A(S) A(S)D15 D9 D8
0
... ...
DEVICE
ADDRESS
REGISTER
ADDRESS
REGISTER
DATA
(SLAVE DRIVE)
REGISTER
DATA
S/P = START/STOP BIT.
A0 = I
2
C R/W BIT.
A(S) = ACKNOWLEDGE BY SLAVE.
A(M) = ACKNOWLEDGE BY MASTER.
A(M) = ACKNOWLEDGE BY MASTER (INVERSION).
06978-022
Figure 25. I
2
C Write and Read Sequences
