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SSM2604CPZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
Data Sheet SSM2604
Rev. A | Page 21 of 28
POWER MANAGEMENT, ADDRESS 0x06
Table 19. Power Management Register Bit Map
D8 D7 D6 D5 D4 D3 D2 D1 D0
0
PWROFF
CLKOUT
OSC
1
DAC
ADC
1
LINEIN
Table 20. Description of Power Management Register Bits
Bit Name Description Settings
PWROFF Whole chip power-down control 0 = power up
1 = power down (default)
CLKOUT Clock output power-down control 0 = power up (default)
1 = power down
OSC
Crystal power-down control
0 = power up (default)
1 = power down
DAC DAC power-down control 0 = power up
1 = power down (default)
ADC ADC power-down control 0 = power up
1 = power down (default)
LINEIN Line input power-down control 0 = power up
1 = power down (default)
Power Consumption
Table 21.
Mode PWROFF CLKOUT OSC DAC ADC LINEIN
AVDD
(3.3 V)
DVDD
(3.3 V)
Unit
Record and Playback 0 0 0 0 0 0 9.41 3.7 mA
Playback Only
Oscillator Enabled
0
0
0
0
1
1
4.45
1.9
mA
External Clock 0 1 1 0 1 1 4.56 1.9 mA
Record Only
Line Clock 0 0 0 1 0 0 4.31 2.0 mA
Line Oscillator 0 0 1 1 0 0 4.33 2.0 mA
Analog Bypass
(Line Input or Line Output)
External Line 0 0 1 1 1 0 1.88 0.21 mA
Internally Generated Line 0 0 1 1 1 0 1.88 0.25 mA
Power-Down
External Clock 1 1 1 1 1 1 0.002 0.015 mA
Oscillator 1 1 1 1 1 1 0.002 0.015 mA
SSM2604 Data Sheet
Rev. A | Page 22 of 28
DIGITAL AUDIO I/F, ADDRESS 0x07
Table 22. Digital Audio I/F Register Bit Map
D8 D7 D6 D5 D4 D3 D2 D1 D0
0
BCLKINV
MS
LRSWAP
LRP
WL [1:0]
FORMAT [1:0]
Table 23. Descriptions of Digital Audio I/F Register Bits
Bit Name Description Settings
BCLKINV BCLK inversion control 0 = BCLK not inverted (default)
1 = BCLK inverted
MS Master mode enable 0 = enable slave mode (default)
1 = enable master mode
LRSWAP
Swap DAC data control
0 = output left- and right-channel data as normal (default)
1 = swap left- and right-channel DAC data in audio interface
LRP Polarity control for clocks in right-justified,
left-justified, and I
2
S modes
0 = normal PBLRC and RECLRC (default), or DSP Submode 1
1 = invert PBLRC and RECLRC polarity, or DSP Submode 2
WL [1:0] Data-word length control 00 = 16 bits
01 = 20 bits
10 = 24 bits (default)
11 = 32 bits
FORMAT [1:0] Digital audio input format control 00 = right justified
01 = left justified
10 = I
2
S mode (default)
11 = DSP mode
SAMPLING RATE, ADDRESS 0x08
Table 24. Sampling Rate Register Bit Map
D8 D7 D6 D5 D4 D3 D2 D1 D0
0 CLKODIV2 CLKDIV2 SR [3:0] BOSR USB
Table 25. Descriptions of Sampling Rate Register Bits
Bit Name Description Settings
CLKODIV2 CLKOUT divider select 0 = CLKOUT is core clock (default)
1 = CLKOUT is core clock divided by 2
CLKDIV2 Core clock divide select 0 = core clock is MCLK (default)
1= core clock is MCLK divided by 2
SR [3:0] Clock setting condition See Table 26 and Table 27
BOSR
Base oversampling rate
USB mode:
0 = support for 250 f
S
based clock (default)
1 = support for 272 f
S
based clock
Normal mode:
0 = support for 256 f
S
based clock (default)
1 = support for 384 f
S
based clock
USB USB mode select 0 = normal mode enable (default)
1 = USB mode enable
Data Sheet SSM2604
Rev. A | Page 23 of 28
Table 26. Sampling Rate Lookup Table, USB Disabled (Normal Mode)
MCLK
(CLKDIV2 = 0)
MCLK
(CLKDIV2 = 1)
ADC Sampling Rate
(RECLRC)
DAC Sampling Rate
(PBLRC) USB SR [3:0] BOSR
BCLK
(MS = 1)
1
12.288 MHz 24.576 MHz 8 kHz (MCLK/1536) 8 kHz (MCLK/1536) 0 0011 0 MCLK/4
8 kHz (MCLK/1536) 48 kHz (MCLK/256) 0 0010 0 MCLK/4
12 kHz (MCLK/1024) 12 kHz (MCLK/1024) 0 0100 0 MCLK/4
16 kHz (MCLK/768) 16 kHz (MCLK/768) 0 0101 0 MCLK/4
24 kHz (MCLK/512) 24 kHz (MCLK/512) 0 1110 0 MCLK/4
32 kHz (MCLK/384) 32 kHz (MCLK/384) 0 0110 0 MCLK/4
48 kHz (MCLK/256) 8 kHz (MCLK/1536) 0 0001 0 MCLK/4
48 kHz (MCLK/256) 48 kHz (MCLK/256) 0 0000 0 MCLK/4
96 kHz (MCLK/128) 96 kHz (MCLK/128) 0 0111 0 MCLK/2
11.2896 MHz 22.5792 MHz 8.0182 kHz (MCLK/1408) 8.0182 kHz (MCLK/1408) 0 1011 0 MCLK/4
8.0182 kHz (MCLK/1408) 44.1 kHz (MCLK/256) 0 1010 0 MCLK/4
11.025 kHz (MCLK/1024) 11.025 kHz (MCLK/1024) 0 1100 0 MCLK/4
22.05 kHz (MCLK/512) 22.05 kHz (MCLK/512) 0 1101 0 MCLK/4
44.1 kHz (MCLK/256) 8.0182 kHz (MCLK/1408) 0 1001 0 MCLK/4
44.1 kHz (MCLK/256) 44.1 kHz (MCLK/256) 0 1000 0 MCLK/4
88.2 kHz (MCLK/128) 88.2 kHz (MCLK/128) 0 1111 0 MCLK/2
18.432 MHz 36.864 MHz 8 kHz (MCLK/2304) 8 kHz (MCLK/2304) 0 0011 1 MCLK/6
8 kHz (MCLK/2304) 48 kHz (MCLK/384) 0 0010 1 MCLK/6
12 kHz (MCLK/1536)
12 kHz (MCLK/1536)
0
0100
1
MCLK/6
16 kHz (MCLK/1152) 16 kHz (MCLK/1152) 0 0101 1 MCLK/6
24 kHz (MCLK/768) 24 kHz (MCLK/768) 0 1110 1 MCLK/6
32 kHz (MCLK/576)
32 kHz (MCLK/576)
0
0110
1
MCLK/6
48 kHz (MCLK/384) 48 kHz (MCLK/384) 0 0000 1 MCLK/6
48 kHz (MCLK/384) 8 kHz (MCLK/2304) 0 0001 1 MCLK/6
96 kHz (MCLK/192) 96 kHz (MCLK/192) 0 0111 1 MCLK/3
16.9344 MHz 33.8688 MHz 8.0182 kHz (MCLK/2112) 8.0182 kHz (MCLK/2112) 0 1011 1 MCLK/6
8.0182 kHz (MCLK/2112) 44.1 kHz (MCLK/384) 0 1010 1 MCLK/6
11.025 kHz (MCLK/1536)
11.025 kHz (MCLK/1536)
0
1100
1
MCLK/6
22.05 kHz (MCLK/768) 22.05 kHz (MCLK/768) 0 1101 1 MCLK/6
44.1 kHz (MCLK/384) 8.0182 kHz (MCLK/2112) 0 1001 1 MCLK/6
44.1 kHz (MCLK/384)
44.1 kHz (MCLK/384)
0
1000
1
MCLK/6
88.2 kHz (MCLK/192) 88.2 kHz (MCLK/192) 0 1111 1 MCLK/3
1
BCLK frequency is for master mode and slave right-justified mode only.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

SSM2604CPZ-REEL

Mfr. #:
Buy SSM2604CPZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs Low Power w/ 24B ADC & 24B DAC
Lifecycle:
New from this manufacturer.
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