SST25PF020B
DS20005135B-page 16 2013 Microchip Technology Inc.
4.5.13 WRITE-DISABLE (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new
Write operations from occurring. The WRDI instruction
will not terminate any programming operation in prog-
ress. Any program operation in progress may continue
up to T
BP
after executing the WRDI instruction. CE#
must be driven high before the WRDI instruction is exe-
cuted.
FIGURE 4-17: WRITE DISABLE (WRDI) SEQUENCE
4.5.14 ENABLE-WRITE-STATUS-
REGISTER (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction
and opens the status register for alteration. The Write-
Status-Register instruction must be executed immedi-
ately after the execution of the Enable-Write-Status-
Register instruction. This two-step instruction
sequence of the EWSR instruction followed by the
WRSR instruction works like SDP (software data pro-
tection) command structure which prevents any acci-
dental alteration of the status register values. CE# must
be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction
is executed.
4.5.15 WRITE-STATUS-REGISTER (WRSR)
The Write-Status-Register instruction writes new val-
ues to the BP1, BP0, and BPL bits of the status register.
CE# must be driven low before the command
sequence of the WRSR instruction is entered and
driven high before the WRSR instruction is executed.
See Figure 4-18 for EWSR or WREN and WRSR for
byte-data input sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”.
When the WP# is low, the BPL bit can only be set from
“0” to “1” to lock-down the status register, but cannot be
reset from “1” to “0”. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
and BP1 bits in the status register can all be changed.
As long as BPL bit is set to 0 or WP# pin is driven high
(V
IH
) prior to the low-to-high transition of the CE# pin at
the end of the WRSR instruction, the bits in the status
register can all be altered by the WRSR instruction. In
this case, a single WRSR instruction can set the BPL
bit to “1” to lock down the status register as well as
altering the BP0, BP1, and BP2 bits at the same time.
See Table 4-1 for a summary description of WP# and
BPL functions.
FIGURE 4-18: ENABLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND
WRITE-STATUS-REGISTER (WRSR) BYTE-DATA INPUT SEQUENCE
CE#
SO
SI
SCK
01234567
04
HIGH IMPEDANCE
MODE 0
MODE 3
25135 WRDI.0
MSB
25135 EWSR.0
MODE 3
HIGH IMPEDANCE
MODE 0
STATUS
REGISTER IN
76543210
MSBMSBMSB
01
MODE 3
SCK
SI
SO
CE#
MODE 0
50 or 06
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
