SST25PF020B
DS20005135B-page 8 2013 Microchip Technology Inc.
4.5 Instructions
Instructions are used to read, write (Erase and Pro-
gram), and configure the SST25PF020B. The instruc-
tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program-
ming, Sector-Erase, Block-Erase, Write-Status-Regis-
ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com-
plete list of instructions is provided in Table 4-5. All
instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of
SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status-
Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com-
mands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.
TABLE 4-5: DEVICE OPERATION INSTRUCTIONS
Instruction Description Op Code Cycle
1
1. One bus cycle is eight clock periods.
Address
Cycle(s)
2
2. Address bits above the most significant bit of each density can be V
IL
or V
IH
.
Dummy
Cycle(s)
Data
Cycle(s)
Read Read Memory 0000 0011b (03H) 301 to ∞
High-Speed Read Read Memory at higher speed 0000 1011b (0BH) 311 to ∞
4 KByte Sector-
Erase
3
3. 4KByte Sector Erase addresses: use A
MS
-A
12,
remaining addresses are don’t care but must be set either at V
IL
or V
IH.
Erase 4 KByte of memory array 0010 0000b (20H) 300
32 KByte Block-
Erase
4
4. 32KByte Block Erase addresses: use A
MS
-A
15,
remaining addresses are don’t care but must be set either at V
IL
or V
IH.
Erase 32 KByte block of memory
array
0101 0010b (52H) 300
64 KByte Block-
Erase
5
5. 64KByte Block Erase addresses: use A
MS
-A
16,
remaining addresses are don’t care but must be set either at V
IL
or V
IH.
Erase 64 KByte block of memory
array
1101 1000b (D8H) 300
Chip-Erase Erase Full Memory Array 0110 0000b (60H) or
1100 0111b (C7H)
000
Byte-Program To Program One Data Byte 0000 0010b (02H) 301
AAI-Word-Program
6
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A
23
-A
1
] with A
0
=0, Data Byte 1 will be pro-
grammed into the initial address [A
23
-A
1
] with A
0
=1.
Auto Address Increment Program-
ming
1010 1101b (ADH) 302 to ∞
RDSR
7
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
Read-Status-Register 0000 0101b (05H) 001 to ∞
RDSR1 Read-Status-Register 1 0011 0101b (35H) 001 to ∞
EWSR Enable-Write-Status-Register 0101b 0000b (50H) 000
WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 or 2
WREN Write-Enable 0000 0110b (06H) 000
WRDI Write-Disable 0000 0100b (04H) 000
RDID
8
8. Manufacturer’s ID is read with A
0
=0, and Device ID is read with A
0
=1. All other address bits are 00H. The Manufacturer’s ID
and Device ID output stream is continuous until terminated by a low-to-high transition on CE#.
Read-ID 1001 0000b (90H) or
1010 1011b (ABH)
301 to ∞
JEDEC-ID JEDEC ID Read 1001 1111b (9FH) 003 to ∞
EBSY Enable SO to output RY/BY# status
during AAI programming
0111 0000b (70H) 000
DBSY Disable SO to output RY/BY# status
during AAI programming
1000 0000b (80H) 000
