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SST25VF040B-80-4I-QAE-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
©2011 Silicon Storage Technology, Inc. DS25051A 09/11
16
4 Mbit SPI Serial Flash
SST25VF040B
Data Sheet
A
Microchip Technology Company
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-
Erase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruc-
tion clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected mem-
ory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed.
CE# must remain active low for the duration of any command sequence. The 32-KByte Block-Erase
instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A
23
-A
0
]. Address
bits [A
MS
-A
15
](A
MS
= Most Significant Address) are used to determine block address (BA
X
), remaining
address bits can be V
IL
or V
IH.
CE# must be driven high before the instruction is executed. The 64-KByte Block-
Erase instruction is initiated by executing an 8-bit command D8H, followed by address bits [A
23
-A
0
]. Address bits
[A
MS
-A
15
] are used to determine block address (BA
X
), remaining address bits can be V
IL
or V
IH.
CE# must be
driven high before the instruction is executed. The user may poll the Busy bit in the software status register or
wait T
BE
for the completion of the internal self-timed 32-KByte Block-Erase or 64-KByte Block-Erase
cycles. See Figures 13 and 14 for the 32-KByte Block-Erase and 64-KByte Block-Erase sequences.
Figure 13:32-KByte Block-Erase Sequence
Figure 14:64-KByte Block-Erase Sequence
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
52
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
1295 32KBklEr.0
MSB MSB
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
D8
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
1295 63KBlkEr.0
MSB MSB
©2011 Silicon Storage Technology, Inc. DS25051A 09/11
17
4 Mbit SPI Serial Flash
SST25VF040B
Data Sheet
A
Microchip Technology Company
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored
if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.
The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven
high before the instruction is executed. The user may poll the Busy bit in the software status register or wait
T
CE
for the completion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase
sequence.
Figure 15:Chip-Erase Sequence
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register
may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in
progress, the Busy bit may be checked before sending any new commands to assure that the new
commands are properly received by the device. CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing
clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR
instruction sequence.
Figure 16:Read-Status-Register (RDSR) Sequence
CE#
SO
SI
SCK
01234567
60 or C7
HIGH IMPEDANCE
MODE 0
MODE 3
1295 ChEr.0
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1295 RDSRseq.0
MODE 3
SCK
SI
SO
CE#
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05
MODE 0
HIGH IMPEDANCE
Status
Register Out
MSB
MSB
©2011 Silicon Storage Technology, Inc. DS25051A 09/11
18
4 Mbit SPI Serial Flash
SST25VF040B
Data Sheet
A
Microchip Technology Company
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit in the Status Register to 1 allow-
ing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/
Erase) operation. The WREN instruction may also be used to allow execution of the Write-Status-Reg-
ister (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared
upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN instruc-
tion is executed.
Figure 17:Write Enable (WREN) Sequence
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any
new Write operations from occurring. The WRDI instruction will not terminate any programming opera-
tion in progress. Any program operation in progress may continue up to T
BP
after executing the WRDI
instruction. CE# must be driven high before the WRDI instruction is executed.
Figure 18:Write Disable (WRDI) Sequence
CE#
SO
SI
SCK
01234567
06
HIGH IMPEDANCE
MODE 0
MODE 3
1295 WREN.0
MSB
CE#
SO
SI
SCK
01234567
04
HIGH IMPEDANCE
MODE 0
MODE 3
1295 WRDI.0
MSB
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SST25VF040B-80-4I-QAE-T

Mfr. #:
Buy SST25VF040B-80-4I-QAE-T
Manufacturer:
Microchip Technology
Description:
NOR Flash 2.7V to 3.6V 4Mbit SPI Serial Flash
Lifecycle:
New from this manufacturer.
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