©2011 Silicon Storage Technology, Inc. DS25051A 09/11
25
4 Mbit SPI Serial Flash
SST25VF040B
Data Sheet
A
Microchip Technology Company
Table 15:AC Operating Characteristics (25VF040B-80-xx-xxxE)
33 MHz 80 MHz
Symbol Parameter Min Max Min Max Units
F
CLK
1
Serial Clock Frequency 33 80 MHz
T
SCKH
Serial Clock High Time 13 6 ns
T
SCKL
Serial Clock Low Time 13 6 ns
T
SCKR
2
Serial Clock Rise Time (Slew Rate) 0.1 0.1 V/ns
T
SCKF
Serial Clock Fall Time (Slew Rate) 0.1 0.1 V/ns
T
CES
3
CE# Active Setup Time 5 5 ns
T
CEH
3
CE# Active Hold Time 5 5 ns
T
CHS
3
CE# Not Active Setup Time 5 5 ns
T
CHH
3
CE# Not Active Hold Time 5 5 ns
T
CPH
CE# High Time 50 50 ns
T
CHZ
CE# High to High-Z Output 7 7 ns
T
CLZ
SCK Low to Low-Z Output 0 0 ns
T
DS
Data In Setup Time 2 2 ns
T
DH
Data In Hold Time 4 4 ns
T
HLS
HOLD# Low Setup Time 5 5 ns
T
HHS
HOLD# High Setup Time 5 5 ns
T
HLH
HOLD# Low Hold Time 5 5 ns
T
HHH
HOLD# High Hold Time 5 5 ns
T
HZ
HOLD# Low to High-Z Output 7 7 ns
T
LZ
HOLD# High to Low-Z Output 7 7 ns
T
OH
Output Hold from SCK Change 0 0 ns
T
V
Output Valid from SCK 10 6 ns
T
SE
Sector-Erase 25 25 ms
T
BE
Block-Erase 25 25 ms
T
SCE
Chip-Erase 50 50 ms
T
BP
Byte-Program 10 10 µs
T15.0 25051
1. Maximum clock frequency for Read Instruction, 03H, is 33 MHz
2. Maximum Rise and Fall time may be limited by T
SCKH
and T
SCKL
requirements
3. Relative to SCK.
©2011 Silicon Storage Technology, Inc. DS25051A 09/11
26
4 Mbit SPI Serial Flash
SST25VF040B
Data Sheet
A
Microchip Technology Company
Figure 22:Serial Input Timing Diagram
Figure 23:Serial Output Timing Diagram
Figure 24:Hold Timing Diagram
HIGH-Z
HIGH-Z
CE#
SO
SI
SCK
MSB
LSB
T
DS
T
DH
T
CHH
T
CES
T
CEH
T
CHS
T
SCKR
T
SCKF
T
CPH
1295 SerIn.0
1295 SerOut.0
CE#
SI
SO
SCK
MSB
T
CLZ
T
V
T
SCKH
T
CHZ
T
OH
T
SCKL
LSB
T
HZ
T
LZ
T
HHH
T
HLS
T
HLH
T
HHS
1295 Hold.0
HOLD#
CE#
SCK
SO
SI
©2011 Silicon Storage Technology, Inc. DS25051A 09/11
27
4 Mbit SPI Serial Flash
SST25VF040B
Data Sheet
A
Microchip Technology Company
Power-Up Specifications
All functionalities and DC specifications are specified for a V
DD
ramp rate of greater than 1V per 100
ms (0v - 3.0V in less than 300 ms). See Table 16 and Figure 25 for more information.
Figure 25:Power-up Timing Diagram
Table 16:Recommended System Power-up Timings
Symbol Parameter Minimum Units
T
PU-READ
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
V
DD
Min to Read Operation 100 µs
T
PU-WRITE
1
V
DD
Min to Write Operation 100 µs
T16.0 25051
Time
V
DD
Min
V
DD
Max
V
DD
Device fully accessible
T
PU-READ
T
PU-WRITE
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
1295 PwrUp.0

SST25VF040B-80-4I-QAE-T

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash 2.7V to 3.6V 4Mbit SPI Serial Flash
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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