OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CY62128EV30LL-45ZAXA

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
CY62128EV30 MoBL
®
Automotive
Document Number: 001-65528 Rev. *E Page 10 of 19
Figure 8. Write Cycle No. 1 (WE Controlled)
[24, 25, 26, 27]
Switching Waveforms (continued)
DATA
IN
VALID
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
ADDRESS
CE
WE
DATA I/O
OE
NOTE
28
Notes
24. The internal write time of the memory is defined by the overlap of WE
, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
25. CE
is the logical combination of CE
1
and CE
2
. When CE
1
is LOW and CE
2
is HIGH, CE is LOW; when CE
1
is HIGH or CE
2
is LOW, CE is HIGH.
26. Data I/O is high impedance if OE
= V
IH
.
27. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
28. During this period, the I/Os are in output state. Do not apply input signals.
CY62128EV30 MoBL
®
Automotive
Document Number: 001-65528 Rev. *E Page 11 of 19
Figure 9. Write Cycle No. 2 (CE
1
or CE
2
Controlled)
[29, 30, 31, 32]
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW)
[29, 32, 33]
Switching Waveforms (continued)
t
WC
DATA
IN
VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
ADDRESS
CE
DATA I/O
WE
DATA
IN
VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
ADDRESS
CE
WE
DATA I/O
NOTE
34
Notes
29. CE
is the logical combination of CE
1
and CE
2
. When CE
1
is LOW and CE
2
is HIGH, CE is LOW; when CE
1
is HIGH or CE
2
is LOW, CE is HIGH
30. The internal write time of the memory is defined by the overlap of WE
, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
31. Data I/O is high impedance if OE
= V
IH
.
32. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
33. The minimum write pulse width should be equal to the sum of t
SD
and t
HZWE
.
34. During this period, the I/Os are in output state. Do not apply input signals.
CY62128EV30 MoBL
®
Automotive
Document Number: 001-65528 Rev. *E Page 12 of 19
Truth Table
CE
1
CE
2
WE OE Inputs/Outputs Mode Power
HX
[35]
X X High Z Deselect/Power-down Standby (I
SB
)
X
[35]
L X X High Z Deselect/Power-down Standby (I
SB
)
L H H L Data out Read Active (I
CC
)
L H L X Data in Write Active (I
CC
)
L H H H High Z Selected, outputs disabled Active (I
CC
)
Note
35. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

CY62128EV30LL-45ZAXA

Mfr. #:
Buy CY62128EV30LL-45ZAXA
Manufacturer:
Cypress Semiconductor
Description:
SRAM 1Mb 3V 45ns 128K x 8 LP SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet