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ADCMP563BCPZ-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15
Dual, High Speed ECL Comparators
Data Sheet
ADCMP563/ADCMP564
Rev. D Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Differential ECL-compatible outputs
700 ps propagation delay input to output
75 ps propagation delay dispersion
Input common-mode range: –2.0 V to +3.0 V
Robust input protection
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 85 dB
700 ps minimum pulse width
1.5 GHz equivalent input rise time bandwidth
Typical output rise/fall time of 500 ps
ESD protection > 4kV HBM, >200V MM
Programmable hysteresis
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Hand-held test instruments
Zero crossing detectors
Line receivers and signal restoration
Clock drivers
GENERAL DESCRIPTION
The ADCMP563/ADCMP564 are high speed comparators
fabricated on Analog Devices’ proprietary XFCB process. The
devices feature a 700 ps propagation delay with less than 75 ps
overdrive dispersion. Dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a partic-
ularly important characteristic of high speed comparators. A separate
programmable hysteresis pin is available on the ADCMP564.
A differential input stage permits consistent propagation delay
with a wide variety of signals in the common-mode range from
−2.0 V to +3.0 V. Outputs are complementary digital signals that
are fully compatible with ECL 10 K and 10 KH logic families.
The outputs provide sufficient drive current to directly drive
transmission lines terminated in 50 Ω to −2 V. A latch input,
which is included, permits tracking, track-and-hold, or sample-
and-hold modes of operation. The latch input pins contain internal
pull-ups that set the latch in tracking mode when left open.
The ADCMP563/ADCMP564 are specified over the industrial
temperature range (−40°C to +85°C).
FUNCTIONAL BLOCK DIAGRAMS
04650-0-001
HYS*
*ADCMP564 ONLY
NONINVERTING
INPUT
INVERTING
INPUT
LATCH ENABLE
INPUT
Q OUTPUT
LATCH ENABLE
INPUT
Q OUTPUT
ADCMP563/
ADCMP564
Figure 1.
04650-0-002
ADCMP563
BRQ
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–INA
+INA
QA
QA
GND
V
EE
LEA
LEA
–INB
+INB
QB
QB
GND
V
CC
LEB
LEB
Figure 2. ADCMP563 16-Lead QSOP
04650-0-012
ADCMP564
BRQ
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
–INA
QA
QA
GND
V
EE
LEA
LEA
GND
+INA
HYSA
–
INB
QB
QB
GND
V
CC
LEB
LEB
GND
+INB
HYSB
Figure 3. ADCMP564 20-Lead QSOP
04650-0-026
12
11
10
1
3
4
9
2
6
5
7
8
16
15
14
13
–INA
+INA
+INB
–INB
QA
QA
QB
QB
V
CC
LEB
LEB
GND
V
EE
LE
A
LEA
GND
ADCMP563
BCP
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED P
AD SHOULD BE EITHER CONNECTED TO VEE OR LEFT FLOATING.
Figure 4. ADCMP563 16-Lead LFCSP
ADCMP563/ADCMP564 Data Sheet
Rev. D | Page 2 of 15
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Considerations .............................................................. 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Timing Information ....................................................................... 10
Application Information ................................................................ 11
Clock Timing Recovery ............................................................. 11
Optimizing High Speed Performance ..................................... 11
Comparator Propagation Delay Dispersion ............................... 11
Comparator Hysteresis .............................................................. 12
Minimum Input Slew Rate Requirement ................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
REVISION HISTORY
4/16—Rev. C to Rev. D
Changes to Figure 4 .......................................................................... 1
Changes to Figure 7 .......................................................................... 6
Updates Outline Dimensions ........................................................ 15
Changes to Ordering Guide .......................................................... 15
6/11—Rev. B to Rev. C
Changes to Figure 4 .......................................................................... 1
Changes to Figure 7 and LFCSP Pin Numbers (Table 3) ............ 6
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
5/05—Rev. A to Rev. B
Added 16-Lead LFCSP ....................................................... Universal
Changes to Applications .................................................................. 1
Changes to Table 1 ............................................................................. 3
Changes to Optimizing High Speed Performance Section ....... 11
Changes to Comparator Hysteresis Section ................................ 12
Changes to Minimum Input Slew Rate Requirement Section . 12
Changes to Ordering Guide .......................................................... 14
7/04—Rev. 0 to Rev. A
Changes to Specification Table ........................................................ 4
Changes to Figure 14 ......................................................................... 9
Changes to Figure 21 ...................................................................... 12
Changes to Figure 23 ...................................................................... 13
4/04—Revision 0: Initial Version
Data Sheet ADCMP563/ADCMP564
Rev. D | Page 3 of 15
SPECIFICATIONS
V
CC
= +5.0 V, V
EE
= −5.2 V, T
A
= −40°C to +85°C. Typical values are at T
A
= +25°C, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Input Voltage Range −2.0 3.0 V
Input Differential Voltage −5 +5 V
Input Offset Voltage V
OS
V
CM
= 0 V −10.0 ±2.0 +10.0 mV
Input Offset Voltage Channel Matching ±2.0 mV
Offset Voltage Temperature Coefficient ∆V
OS
/d
T
2.0 µV/°C
I
BC
@ −IN = −2 V, +IN = +3 V
−10.0
±3
+10.0
µA
Input Bias Current Temperature Coefficient 0.5 nA/°C
Input Offset Current ±1.0 µA
Input Capacitance C
IN
0.75 pF
Input Resistance, Differential Mode 750 kΩ
Input Resistance, Common Mode 1800 kΩ
Active Gain A
V
63 dB
Common-Mode Rejection Ratio CMRR V
CM
= −2.0 V to +3.0 V 80 dB
Hysteresis R
HYS
= ∞ ±1.0 mV
LATCH ENABLE CHARACTERISTICS
Latch Enable Voltage Range −2.0 0 V
Latch Enable Differential Input Voltage 0.4 2.0 V
Latch Enable Input High Current @ 0.0 V −300 +300 µA
Latch Enable Input Low Current @ −2.0 V −300 +300 µA
Latch inputs not connected
−0.2
0
+0.1
V
LE
Voltage, Open Latch inputs not connected −2.8 −2.6 −2.4 V
Latch Setup Time t
S
V
OD
= 250 mV 200 ps
Latch Hold Time t
H
V
OD
= 250 mV 200 ps
Latch to Output Delay t
PLOH
,
t
PLOL
V
OD
= 250 mV 500 ps
Latch Minimum Pulse Width t
PL
V
OD
= 250 mV 500 ps
DC OUTPUT CHARACTERISTICS
Output Voltage—High Level V
OH
ECL 50 Ω to −2.0 V −1.15 −0.81 V
Output Voltage—Low Level V
OL
ECL 50 Ω to −2.0 V −1.95 −1.54 V
Rise Time t
R
10% to 90% 530 ps
Fall Time t
F
10% to 90% 450 ps
AC PERFORMANCE
Propagation Delay t
PD
V
OD
= 1 V 700 ps
V
OD
= 20 mV 830 ps
Propagation Delay Temperature Coefficient ∆t
PD
/d
T
V
OD
= 1 V 0.25 ps/°C
Prop Delay Skew—Rising Transition to Falling
Transition
V
OD
= 1 V 50 ps
Within Device Propagation Delay Skew—
Channel-to-Channel
V
OD
= 1 V 50 ps
Overdrive Dispersion 20 mV ≤ V
OD
≤ 100 mV 75 ps
100 mV ≤ V
OD
≤ 1.5 V 75 ps
0.4 V/ns ≤ SR ≤ 1.33 V/ns
50
ps
Pulse Width Dispersion 750ps ≤ PW ≤ 10 ns 25 ps
Duty Cycle Dispersion 33 MHz, 1 V/ns, 0.5 V 10 ps
Common-Mode Voltage Dispersion 1 V swing, −1.5 V ≤ V
CM
≤ +2.5 V 10 ps
P1-P3P4-P6P7-P9P10-P12P13-P15

ADCMP563BCPZ-RL7

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Analog Comparators IC Dual High Spd ECL
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