ADCMP563/ADCMP564 Data Sheet
Rev. D | Page 4 of 15
Parameter Symbol Conditions Min Typ Max Unit
AC PERFORMANCE (Continued)
Equivalent Input Rise Time Bandwidth
1
BW
EQ
0 V to 1 V swing, 2 V/ns 1500 MHz
Maximum Toggle Rate >50% output swing, 50% duty cycle 800 MHz
Minimum Pulse Width PW
MIN
Δt
PD
< 25 ps 700 ps
V
OD
= 400 mV, 1.3 V/ns, 312 MHz,
50% duty cycle
1.0
ps
Unit to Unit Propagation Delay Skew 100 ps
Positive Supply Current I
VCC
@ +5.0 V 2 3.2 5 mA
Negative Supply Current I
VEE
@ 5.2 V 10 19 25 mA
Positive Supply Voltage V
CC
Dual 4.75 5.0 5.25 V
Negative Supply Voltage V
EE
Dual 4.96 5.2 5.45 V
Power Dissipation P
D
Dual, without load 90 120 150 mW
Dual, with load 150 180 230 mW
DC Power Supply Rejection Ratio—V
CC
PSRR
VCC
85 dB
DC Power Supply Rejection Ratio—V
EE
PSRR
VEE
85 dB
HYSTERESIS (ADCMP564 Only)
Hysteresis R
HYS
= 23.5 kΩ 20 mV
R
HYS
= 9.0 kΩ 70 mV
Hysteresis Pin Bias Voltage Referred to AGND −1 V
Hysteresis Pin Series Resistance 3 kΩ
1
Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BW
EQ
= 0.22/√(tr
COMP
2
tr
IN
2
), where tr
IN
is the
20/80 input transition time applied to the comparator and tr
COMP
is the effective transition time, as digitized by the comparator input.
Data Sheet ADCMP563/ADCMP564
Rev. D | Page 5 of 15
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltages
Positive Supply Voltage (V
CC
to GND) 0.5 V to +6.0 V
Negative Supply Voltage (V
EE
to GND) 6.0 V to +0.5 V
Ground Voltage Differential 0.5 V to +0.5 V
Input Voltages
Input Common-Mode Voltage 3.0 V to +4.0 V
Differential Input Voltage 7.0 V to +7.0 V
Input Voltage, Latch Controls V
EE
to +0.5 V
Output
Output Current 30 mA
Temperature
Operating Temperature, Ambient 40°C to +85°C
Operating Temperature, Junction 125°C
Storage Temperature Range 65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CONSIDERATIONS
The ADCMP563 QSOP 16-lead package option has a θ
JA
(junction-to-ambient thermal resistance) of 104°C/W in
still air.
The ADCMP563 LFCSP 16-lead package option has a θ
JA
(junction-to-ambient thermal resistance) of 70°C/W in
still air.
The ADCMP564 QSOP 20-lead package option has a θ
JA
(junction-to-ambient thermal resistance) of 80°C/W in
still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADCMP563/ADCMP564 Data Sheet
Rev. D | Page 6 of 15
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04650-0-002
ADCMP563
BRQ
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–INA
+INA
QA
QA
GND
V
EE
LEA
LEA
–INB
+INB
QB
QB
GND
V
CC
LEB
LEB
Figure 5. ADCMP563 16-Lead QSOP
Pin Configuration
04650-0-012
ADCMP564
BRQ
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
–INA
QA
QA
GND
V
EE
LEA
LEA
GND
+INA
HYSA
–INB
QB
QB
GND
V
CC
LEB
LEB
GND
+INB
HYSB
Figure 6. ADCMP564 20-Lead QSOP
Pin Configuration
12
11
10
1
3
4
9
2
6
5
7
8
16
15
14
13
–INA
+INA
+INB
–INB
QA
QA
QB
QB
V
CC
LEB
LEB
GND
V
EE
LEA
LE
A
GND
ADCMP563
BCP
T
OP
VIEW
(Not to Scale)
NOTES
1. THE EXPOSED
PAD SHOULD BE EITHER CONNECTED TO VEE OR LEFT FLOATING.
Figure 7. ADCMP563 16-Lead LFCSP
Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
ADCMP563
16-Lead
QSOP
ADCMP563
16-Lead
LFCSP
ADCMP564
20-Lead
QSOP
Mnemonic
Function
1 GND Analog Ground.
1 11 2 QA One of Two Complementary Outputs for Channel A. QA is logic high if the
analog voltage at the noninverting input is greater than the analog voltage
at the inverting input (provided the comparator is in compare mode). See
the description of the LEA pin for more information.
2 12 3
QA
One of Two Complementary Outputs for Channel A.
QA
is logic low if the
analog voltage at the noninverting input is greater than the analog voltage
at the inverting input (provided the comparator is in compare mode). See
the description of the LEA pin for more information.
3 13 4 GND Analog Ground.
4 14 5 LEA One of Two Complementary Inputs for Channel A Latch Enable. In compare
mode (logic high), the output tracks change at the input of the comparator.
In latch mode (logic low), the output reflects the input state just prior to the
comparator being placed in the latch mode.
LEA
must be driven in
conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
5 15 6
LEA
One of Two Complementary Inputs for Channel A Latch Enable. In compare
mode (logic low), the output tracks change at the input of the comparator.
In latch mode (logic high), the output reflects the input state just prior to the

ADCMP563BCPZ-RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators IC Dual High Spd ECL
Lifecycle:
New from this manufacturer.
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