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ADCMP563BCPZ-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15
Data Sheet ADCMP563/ADCMP564
Rev. D | Page 7 of 15
Pin No.
ADCMP563
16-Lead
QSOP
ADCMP563
16-Lead
LFCSP
ADCMP564
20-Lead
QSOP Mnemonic Function
comparator being placed in the latch mode. LEA must be driven in
conjunction with
LEA
. If left unconnected, the comparator defaults to
compare mode.
6 16 7 V
EE
Negative Supply Terminal.
7 1 8 −INA Inverting Analog Input of the Differential Input Stage for Channel A. The
Inverting A input must be driven in conjunction with the Noninverting A input.
8 2 9 +INA Noninverting Analog Input of the Differential Input Stage for Channel A. The
Noninverting A input must be driven in conjunction with the Inverting A input.
10 HYSA Programmable Hysteresis Input.
11 HYSB Programmable Hysteresis Input.
9 3 12 +INB Noninverting Analog Input of the Differential Input Stage for Channel B. The
Noninverting B input must be driven in conjunction with the Inverting B input.
10 4 13 −INB Inverting Analog Input of the Differential Input Stage for Channel B. The
Inverting B input must be driven in conjunction with the Noninverting B input.
11 5 14 V
CC
Positive Supply Terminal.
12 6 15
LEB
One of Two Complementary Inputs for Channel B Latch Enable. In compare
mode (logic low), the output tracks change at the input of the comparator.
In latch mode (logic high), the output reflects the input state just prior to the
comparator being placed in the latch mode. LEB must be driven in conjunction
with
LEB
. If left unconnected, the comparator defaults to compare mode.
13 7 16 LEB One of Two Complementary Inputs for Channel B Latch Enable. In compare
mode (logic high), the output tracks change at the input of the comparator.
In latch mode (logic low), the output reflects the input state just prior to the
comparator being placed in the latch mode.
LEB
must be driven in conjunction
with LEB. If left unconnected, the comparator defaults to compare mode.
14 8 17 GND Analog Ground.
15 9 18
QB
One of Two Complementary Outputs for Channel B.
QB
is logic low if the
analog voltage at the noninverting input is greater than the analog voltage
at the inverting input (provided the comparator is in compare mode). See
the description of the LEB pin for more information.
16 10 19 QB One of Two Complementary Outputs for Channel B. QB is logic high if the
analog voltage at the noninverting input is greater than the analog voltage
at the inverting input (provided the comparator is in compare mode). See the
description of the LEB pin for more information.
20 GND Analog Ground.
EPAD
EPAD
Exposed Pad. The exposed pad should be either connected to VEE or left
floating.
ADCMP563/ADCMP564 Data Sheet
Rev. D | Page 8 of 15
TYPICAL PERFORMANCE CHARACTERISTICS
V
CC
= 3.3 V, T
A
= 25°C, unless otherwise noted.
3.0
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
–2.5 –1.5 –0.5 0.5 1.5 2.5 3.5
04650-0-013
NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0V)
INPUT BIAS CURRENT (µA)
Figure 8. Input Bias Current vs. Input Voltage
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
–40
–20
0
20 40
60 80
04650-0-014
TEMPERATURE (
°C)
OFFSET VOLTAGE (mV)
Figure 9. Input Offset Voltage vs. Temperature
550
500
505
510
515
520
525
530
535
540
545
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
04650-0-015
TEMPERATURE (°C)
TIME (ps)
Figure 10. Rise Time vs. Temperature
2.80
2.78
2.76
2.74
2.72
2.70
2.68
2.66
2.64
2.62
2.60
–40 –20 0 20 40 60 80
04650-0-016
TEMPERATURE (°C)
+IN INPUT BIAS CURRENT (µA)
(+IN = 3V, –IN = 0V)
Figure 11. Input Bias Current vs. Temperature
–0.8
–2.0
–1.8
–1.6
–1.4
–1.2
–1.0
0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
04650-0-017
TIME (ns)
OUTPUT RISE AND FALL (V)
Figure 12. Rise and Fall of Outputs vs. Time
475
470
465
460
455
450
445
440
435
430
425
–40 –30
–20 –10 0 10
20 30 40 50 60 70 80
90
04650-0-018
TEMPERATURE (°C)
TIME (ps)
Figure 13. Fall Time vs. Temperature
Data Sheet ADCMP563/ADCMP564
Rev. D | Page 9 of 15
720
715
710
705
700
695
690
685
680
–40 –30 –20 –10 0 10 20 30 40 50
60
70 80
90
04650-0-019
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
Figure 14. Propagation Delay vs. Temperature
140
120
100
80
60
40
20
0
0
1.61.41.21.00.8
0.60.40.2
04650-0-020
OVERDRIVE VOLTAGE (V)
PROPAGATION DELAY ERROR (ps)
Figure 15. Propagation Delay Error vs. Overdrive Voltage
160
140
120
100
80
60
40
20
0
50 010203040
04650-0-021
R
HYS
(kΩ)
PROGRAMMED HYSTERESIS (mV)
Figure 16. Comparator Hysteresis vs. R
HYS
705
704
703
702
701
700
699
698
697
–2 –1
0 1
2
3
04650-0-022
INPUT COMMON-MODE VOLTAGE (V)
PROPAGATION DELAY (ps)
Figure 17. Propagation Delay vs. Common-Mode Voltage
25
–5
0
5
10
15
20
0.7 1.7
2.7 3.7 4.7 5.7 6.7 7.7 8.7 9.7
04650-0-023
PULSE WIDTH (ns)
PROPAGATION DELAY ERROR (ps)
Figure 18. Propagation Delay Error vs. Pulse Width
160
140
120
100
80
60
40
20
0
0 50 100 150
04650-0-024
I
HYS
(µA)
PROGRAMMED HYSTERESIS (mV)
Figure 19. Comparator Hysteresis vs. I
HYS
P1-P3P4-P6P7-P9P10-P12P13-P15

ADCMP563BCPZ-RL7

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Buy ADCMP563BCPZ-RL7
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators IC Dual High Spd ECL
Lifecycle:
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