AD7721
REV. A
–15–
CS
AD7721
DRDY
WR
RD
CS
1Y1
1Y2
1Y3
2Y1
2Y2
2Y3
2Y4
HC244
1G 2G
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y4
1Y1
1Y2
1Y3
2A1
2A2
2A3
2A4
HC244
1G 2G
1A1
1A2
1A3
1A4
2Y1
2Y2
2Y3
2Y4
1Y4
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
EN
ADDR
DECODE
A15–A0
D11–D0
TMS320C20/
C25
RD/
W
IRQ
IS
STRB
Figure 19. AD7721 to TMS320C20/C25 Interface
CS
AD7721
DRDY
WR
RD
CS
1Y1
1Y2
1Y3
2Y1
2Y2
2Y3
2Y4
HC244
1G 2G
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y4
1Y1
1Y2
1Y3
2A1
2A2
2A3
2A4
HC244
1G 2G
1A1
1A2
1A3
1A4
2Y1
2Y2
2Y3
2Y4
1Y4
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RD
IRQ
WE
DMA13–DMA0
DMD11–DMD
IS
TMS320C5x
EN
ADDR
DECODE
Figure 20. AD7721 to TMS320C5x Interface
Grounding and Layout
Since the analog inputs are differential, most of the voltages in
the analog modulator are common-mode voltages. The excellent
common-mode rejection of the part will remove common-mode
noise on these inputs. The analog and digital supplies to the
AD7721 are independent and separately pinned out to minimize
coupling between analog and digital sections of the device. The
digital filter will provide rejection of broadband noise on the
power supplies, except at integer multiples of the modulator
sampling frequency. The digital filter also removes noise from
the analog inputs provided the noise source does not saturate
the analog modulator. As a result, the AD7721 is more immune
to noise interference than a conventional high resolution con-
verter. However, because the resolution of the AD7721 is high
and the noise levels from the AD7721 so low, care must be
taken with regard to grounding and layout.
The printed circuit board that houses the AD7721 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. Digital and analog ground planes should only be
joined in one place. If the AD7721 is the only device requiring
an AGND to DGND connection, the ground planes should be
connected at the AGND and DGND pins of the AD7721.
DSUBST, which is the substrate connection for the digital
circuitry of the AD7721, should be connected directly to
AGND. If the AD7721 is in a system where multiple devices
require AGND to DGND connections, the connection should
still be made at one point only, a star ground point that should
be established as close as possible to the AD7721.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7721 to avoid noise coupling. The power
supply lines to the AD7721 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This will reduce the
effects of feedthrough through the board. A microstrip tech-
nique is by far the best but is not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes while signals are placed on the
other side.
Good decoupling is important when using high resolution
ADCs. All analog and digital supplies should be decoupled to
AGND and DGND respectively with 10 nF ceramic capacitors
in parallel with 1 µF tantalum capacitors. To achieve the best
from these decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against the device. In
systems where a common supply voltage is used to drive both
the AV
DD
and DV
DD
of the AD7721, it is recommended that
the system’s AV
DD
supply is used. This supply should have the
recommended analog supply decoupling between the AV
DD
pin
of the AD7721 and AGND and the recommended digital supply
decoupling capacitor between the DV
DD
pins and DGND.
