OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7721ARZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
SPECIFICATIONS
1
Parameter A Version S Version Units Test Conditions/Comments
PARALLEL MODE ONLY
STATIC PERFORMANCE
Resolution 12 12 Bits
Minimum Resolution for Which 12 12 Bits min Guaranteed 12 Bits Monotonic
No Missing Codes Is Guaranteed
Differential Nonlinearity ±1/2 ±1/2 LSB typ
Integral Nonlinearity ±1/2 ±1/2 LSB typ 12-Bit Operation
DC CMRR 70 70 dB min Bipolar Mode
Offset Error
2
Unipolar Mode ±3.66 ±3.66 mV max Typically 0.61 mV
Bipolar Mode ±3.66 ±3.66 mV max Typically 0.61 mV
Full-Scale Error
2, 3
Unipolar Mode ±4.88 ±4.88 mV max Typically 0.61 mV
Bipolar Mode ±4.88 ±4.88 mV max Typically 1.22 mV
Unipolar Offset Drift 0.04 0.04 mV/°C typ
Bipolar Offset Drift 0.035 0.035 mV/°C typ
ANALOG INPUTS
Signal Input Span (VIN1–VIN2):
Bipolar Mode ±V
REFIN
/2 ±V
REFIN
/2 Volts max UNI = V
IH
Unipolar Mode 0 to V
REFIN
0 to V
REFIN
Volts max UNI = V
IL
Maximum Input Voltage AV
DD
AV
DD
Volts
Minimum Input Voltage 0 0 Volts
Input Sampling Capacitance 1.6 1.6 pF typ
Input Sampling Rate 2 f
CLK
2 f
CLK
MHz Guaranteed by Design
Differential Input Impedance 31.25 31.25 kΩ typ With 10 MHz on CLK Pin
REFERENCE INPUTS
V
REFIN
2.4 to 2.6 2.4 to 2.6 V min/V max
REFIN Input Current 200 200 µA typ
DYNAMIC SPECIFICATIONS
Signal to (Noise + Distortion) 70 70 dB min Input Bandwidth 0 kHz to 140 kHz
Total Harmonic Distortion –78 –78 dB max Input Bandwidth 0 kHz to 152.8 kHz
Frequency Response
0 kHz–140 kHz ±0.05 ±0.05 dB max
152.8 kHz –3 –3 dB min
172.67 kHz to 9.827 MHz –72 –72 dB min
CLOCK
CLK Duty Ratio 45 to 55 45 to 55 % max For Specified Operation
V
CLKH
, CLK High Voltage 0.7 × DV
DD
0.7 × DV
DD
V min CLK Uses CMOS Logic
V
CLKL
, CLK Low Voltage 0.3 × DV
DD
0.3 × DV
DD
V max
LOGIC INPUTS
V
INH
, Input High Voltage 2.0 2.0 V min
V
INL
, Input Low Voltage 0.8 0.8 V max
I
INH
, Input Current 10 10 µA max
C
IN
, Input Capacitance 10 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage 4.0 4.0 V min |I
OUT
| ≤ 200 µA
V
OL
, Output Low Voltage 0.4 0.4 V max |I
OUT
| ≤ 1.6 mA
POWER SUPPLIES
AV
DD
4.75/5.25 4.75/5.25 V min/V max
DV
DD
4.75/5.25 4.75/5.25 V min/V max
I
DD
(Total from AV
DD
, DV
DD
) 28.5 28.5 mA max
Digital Inputs Equal to 0 V or DV
DD
Power Consumption 150 150 mW max Active Mode
Power Consumption 100 100 µW max Standby Mode
NOTES
1
Operating temperature range is as follows: A Version: –40°C to +85°C; S Version: –55°C to +125°C.
2
Applies after calibration at temperature of interest.
3
Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin.
Specifications subject to change without notice.
–3–
REV. A
(AV
DD
= +5 V 6 5%; DV
DD
= +5 V 6 5%; AGND = DGND = 0 V, f
CLK
= 10 MHz,
REFIN = +2.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
AD7721
AD7721
REV. A
–4–
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Parameter (A, S Versions) Units Conditions/Comments
Serial Interface
f
CLK
3
100 kHz min Master Clock Frequency
15 MHz max 15 MHz for Specified Performance
t
CLK LO
0.45 × t
CLK
ns min Master Clock Input Low Time
t
CLK HI
0.45 × t
CLK
ns min Master Clock Input High Time
t
1
t
CLK
ns nom DRDY High Time
t
2
4
t
CLK HI
– 10 ns min RFS Low to SCLK Falling Edge Setup Time
t
3
20 ns max RFS Low to Data Valid Delay
t
4
t
CLK HI
ns nom SCLK High Pulse Width
t
5
t
CLK LO
ns nom SCLK Low Pulse Width
t
6
25 ns max SCLK Rising Edge to Data Valid Delay
t
7
0 ns min RFS to SCLK Falling Edge Hold Time
t
8
5
0 ns min Bus Relinquish Time after Rising Edge of RFS
20 ns max
t
9
32 × t
CLK
ns nom Period between Consecutive DRDY Rising Edges
Parallel Interface
f
CLK
3
100 kHz min Master Clock Frequency
10 MHz max 10 MHz for Specified Performance
t
CLK LO
0.45 × t
CLK
ns min Master Clock Input Low Time
t
CLK HI
0.45 × t
CLK
ns min Master Clock Input High Time
Read Operation
t
10
2 × t
CLK
ns nom DRDY High Time
t
11
30 ns max Data Access Time after Falling Edge of DRDY
t
12
32 × t
CLK
ns nom Period between Consecutive DRDY Rising Edges
Write Operation
t
13
35 ns min WR Pulse Width
t
14
20 ns min Data Valid to WR High Setup Time
t
15
0 ns min Data Valid to WR High Hold Time
NOTES
The timing is measured with a load of 50 pF on SCLK and DRDY. SCLK can be operated with a load capacitance of 50 pF maximum.
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
All digital outputs are timed with the load circuit below and, except for t
2
, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last.
3
The AD7721 is production tested with f
CLK
at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by character-
ization to operate with CLK frequencies down to 100 kHz.
4
t
2
is the time from RFS crossing 1.6 V to SCLK crossing 0.8 V.
5
t
8
and t
15
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus
relinquish time of the part and, as such, is independent of external bus loading capacitance.
TO
OUTPUT
PIN
+1.6V
I
OH
I
OL
C
L
50pF
1.6mA
200mA
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
(AV
DD
= +5 V 6 5%; DV
DD
= +5 V 6 5%; AGND = DGND = 0 V, REFIN= +2.5 V
unless otherwise noted)
AD7721
REV. A
–5–
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise stated)
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . –0.3 V to DV
DD
+ 0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AV
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . . ±10 mA
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Plastic Package
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . +260°C
Cerdip Package
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 51°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . +300°C
SOIC Package
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 72°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latchup.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model Temperature Range Package Option*
AD7721AN –40°C to +85°C N-28
AD7721AR –40°C to +85°C R-28
AD7721SQ –55°C to +125°C Q-28
*N = Plastic DIP; R = 0.3" Small Outline IC (SOIC); Q = Cerdip.
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD7721
SCLK/DB7
DVAL/SYNC
WR
RD
DB6
DB8
DB9
RFS
/DB10
VIN1
VIN2
AGND
SDATA/DB11
DGND
DSUBST
DGND
STBY/DB0
DV
DD
AV
DD
AGND
REFIN
CAL/DB1
UNI
/DB2
DB3
DB4
CS
SYNC/DB5
DRDY
CLK
WARNING!
ESD SENSITIVE DEVICE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD7721ARZ

Mfr. #:
Buy AD7721ARZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 12-/16-Bit 312.5kHz/468.75kHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet