AD7721ARZ Datasheet AD7721ARZ, AD7721ARZ-REEL, AD7721AR | P7-P9

AD7721

REV. A

–6–

PIN FUNCTION DESCRIPTIONS

Mnemonic Function

Analog Positive Supply Voltage, +5 V ± 5%.

AGND Ground reference point for analog circuitry.

Digital Supply Voltage, +5 V ± 5%.

DGND Ground reference point for digital circuitry. DGND must be connected via its own short path to AGND (Pin 24).

DSUBST This is the substrate connection for digital circuits. It must be connected via its own short path to AGND

(Pin 24).

VIN1 Analog Input. In unipolar operation, the analog input range on VIN1 is VIN2 to (VIN2 + V

REFIN

); for bipolar

VIN2 operation, the analog input range on VIN1 is (VIN2 ± V

REFIN

/2). The absolute analog input range must lie

between 0 and AV

. The analog input is continuously sampled and processed by the analog modulator.

REFIN Reference Input. The AD7721 operates with an external reference, of value 2.5 V nominal. A suitable refer-

ence for operation with the AD7721 is the AD780. A 100 nF decoupling capacitor is required between

REFIN and AGND.

CLK CMOS Logic Clock Input. The AD7721 operates with an external clock which is connected to the CLK pin.

The modulator samples the analog input on both phases of the clock, increasing the sampling rate to 20 MHz

(CLK = 10 MHz) or 30 MHz (CLK = 15 MHz).

Serial Mode Only

CS, RD, WR To select the serial interface mode of operation, the AD7721 must be powered up with CS, RD and WR all

tied to DGND. After two clock cycles, the AD7721 switches into serial mode. These pins must remain low

during serial operation.

DRDY In the serial interface mode, a rising edge on DRDY indicates that new data is available to be read from the

interface. During a synchronization or calibration cycle,

DRDY remains low until valid data is available.

SDATA/DB11 Serial Data Output. Output serial data becomes active after

RFS goes low. Sixteen bits of data are clocked

out starting with the MSB. Serial data is clocked out on the rising edge of SCLK and is valid on the subse-

quent falling edge of SCLK.

RFS/DB10 Receive Frame Synchronization. Active low logic input. This is a logic input with RFS provided by connect-

ing this input to

DRDY. When RFS is high, SDATA is high impedance.

DB9 This is a test mode pin. This pin must be tied to DGND.

DB8 This is a test mode pin. This pin must be tied to DGND.

SCLK/DB7 Serial Clock. Logic Output. The internal digital clock is provided as an output on this pin. Data is output

from the AD7721 on the rising edge of SCLK and is valid on the falling edge of SCLK.

DB6 This is a test mode pin. This pin must be tied to DGND.

SYNC/DB5 Synchronization Logic Input. A rising edge on SYNC starts the synchronization cycle. SYNC must be

pulsed low for at least one clock cycle to initiate a synchronization cycle.

DB4 This is a test mode pin. This pin must be tied to DGND.

DB3 This is a test mode pin. This pin must be tied to DGND.

UNI/DB2 Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A logic high selects

bipolar mode.

CAL/DB1 Calibration Mode Logic Input. CAL must go high for at least one clock cycle to initiate a calibration cycle.

STBY/DB0 Standby Mode Logic Input. A logic high on this pin selects standby mode.

DVAL/SYNC Data Valid Digital Output. In serial mode, this pin is a dedicated data valid pin.

AD7721

REV. A

–7–

Parallel Mode Only

Mnemonic Function

CS Chip Select Logic Input.

RD Read Logic Input. This digital input is used in conjunction with CS to read data from the device.

WR Write Logic Input. This digital input is used in conjunction with CS to write data to the control register.

DRDY In parallel interface mode, a falling edge on DRDY indicates that new data is available to be read from the

interface. During a synchronization or calibration cycle,

DRDY remains high until valid data is available.

DVAL/

SYNC The function of this pin is determined by the state of bit DB3 in the control register. Writing a logic zero to

bit DB3 will program this pin to be a DVAL output. Writing a logic one to bit DB3 will program this pin to

be a

SYNC input pin.

A rising edge on

SYNC starts the synchronization cycle. SYNC must be pulsed low for at least one clock

cycle.

When switching this pin from

SYNC mode to DVAL mode, it is important that there are no rising edges on

the pin which could cause resynchronization. For this purpose, an internal pull-up resistor has been included

on this pin. Thus, when the external driver driving this pin in

SYNC mode is switched off, the DVAL/SYNC

pin remains high.

SDATA/DB11– These pins are both data outputs and control register inputs. Output data is placed on these pins by taking

STBY/DB0

RD and CS low. Data on these pins is read into the control register by toggling WR low with CS low. With

RD high, these pins are high impedance.

Control functions such as CAL,

UNI and STBY, which are available as pins in serial mode, are available as bits in parallel mode.

Table I lists the contents of the control register onboard the AD7721. This register is written to in parallel mode using the

WR pin.

Table I. Function of Control Register Bits

Control

Bit Function State Mode

DB0 STBY 0 Normal Operation.

1 Power-Down (Standby) Mode.

DB1 CAL 0 Normal Operation.

1 Writing a Logic “1” to this bit starts a calibration cycle. Internal logic resets this bit to zero at the end of

calibration.

DB2 UNI 0 Unipolar Mode.

1 Bipolar Mode.

DB3 DVAL/SYNC 0 Sets DVAL/SYNC Pin to DVAL Mode.

1 Sets DVAL/SYNC Pin to SYNC Mode.

DB9 0 This bit is used for testing the AD7721. A logic low MUST be written into this bit for normal

operation.

AD7721

REV. A

–8–

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. The end-

points of the transfer function are zero scale (not to be con-

fused with bipolar zero), a point 0.5 LSB below the first code

transition (100 . . . 00 to 100 . . . 01 in bipolar mode and

000 . . . 00 to 000 . . . 01 in unipolar mode) and full scale, a point

0.5 LSB above the last code transition (011 . . . 10 to 011 . . . 11 in

bipolar mode and 111 . . . 10 to 111 . . . 11 in unipolar mode). The

error is expressed in LSBs.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between two adjacent codes in the ADC.

Common Mode Rejection Ratio

The ability of a device to reject the effect of a voltage applied to

both input terminals simultaneously—often through variation of

a ground level—is specified as a common-mode rejection ratio.

CMRR is the ratio of gain for the differential signal to the gain

for the common-mode signal.

Unipolar Offset Error

Unipolar offset error is the deviation of the first code transition

from the ideal VIN1 voltage which is (VIN2 + 0.5 LSB) when

operating in the unipolar mode.

Bipolar Offset Error

This is the deviation of the midscale transition (111 . . . 11

to 000 . . . 00) from the ideal VIN1 voltage which is (VIN2 –

0.5 LSB) when operating in the bipolar mode.

Unipolar Full-Scale Error

Unipolar full-scale error is the deviation of the last code transition

(111 . . . 10 to 111 . . . 11) from the ideal VIN1 voltage which is

(VIN2 + V

REFIN

– 3/2 LSBs).

Bipolar Full-Scale Error

The bipolar full-scale error refers to the positive full-scale error and

the negative full-scale error. The positive full-scale error is the

deviation of the last code transition (011 . . . 10 to 011 . . . 11) from

the ideal VIN1 voltage which is (VIN2 + V

REFIN

/2 – 3/2 LSB).

The negative full-scale error is the deviation of the first code transi-

tion (100 . . . 00 to 100 . . . 01) from the ideal VIN1 voltage which

is (VIN2 – V

REFIN

/2 + 0.5 LSB).

Signal to (Noise + Distortion)

Signal to (Noise + Distortion) is measured signal to noise at the

output of the ADC. The signal is the rms magnitude of the funda-

mental. Noise is the rms sum of all the nonfundamental signals up

to half the sampling frequency (f

CLK

/2) but excluding the dc com-

ponent. Signal to (Noise + Distortion) is dependent on the num-

ber of quantization levels used in the digitization process; the more

levels, the smaller the quantization noise. The theoretical Signal to

(Noise + Distortion) ratio for a sine wave input is given by

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

where N is the number of bits. Thus, for an ideal 12-bit converter,

Signal to (Noise + Distortion) = 74 dB.

Total Harmonic Distortion

Total Harmonic Distortion (THD) is the ratio of the rms sum

of harmonics to the rms value of the fundamental. For the

AD7721, THD is defined as

THD = 20 log

)

where V

is the rms amplitude of the fundamental and V

, V

and V

are the rms amplitudes of the second through the

sixth harmonic.

USING THE AD7721

ADC Differential Inputs

The AD7721 uses differential inputs to provide common-mode

noise rejection. In the bipolar mode configuration, the analog

input range is ±1.25 V. The designed code transitions occur

midway between successive integer LSB values. The output

code is 2s complement binary with 1 LSB = 0.61 mV in paral-

lel mode and 38 µV in serial mode. The ideal input/output

transfer function is illustrated in Figure 2.

In the unipolar mode, the analog input range is 0 V to 2.5 V.

Again, the designed code transitions occur midway between suc-

cessive integer LSB values. The output code is straight binary with

1 LSB = 0.61 mV in parallel mode and 38 µV in serial mode. The

ideal input/output transfer function is shown in Figure 3.

100...000

011...111

000...000

011...110

000...010

000...001

111...111

111...110

100...001

DIFFERENTIAL INPUT VOLTAGE (VIN1–VIN2)

OUTPUT

CODE

AD7721

–REF IN/2

+REF IN/2–1LSB

Figure 2. AD7721 Bipolar Mode Transfer Function

000...000

000...010

000...001

111...111

111...110

DIFFERENTIAL INPUT VOLTAGE (VIN1–VIN2)

OUTPUT

CODE

AD7721

111...101

111...100

000...011

0V REF IN–1LSB

Figure 3. AD7721 Unipolar Mode Transfer Function

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD7721ARZ

Mfr. #:

Buy AD7721ARZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 12-/16-Bit 312.5kHz/468.75kHz

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AD7721ARZ

AD7721ARZ

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