AD7621
Rev. 0 | Page 15 of 32
THEORY OF OPERATION
04565-024
SW+
COMP
SW–
IN+
REF
REFGND
LSB
MSB
32,768C 16,384C 4C 2C C C
SWITCHES
CONTROL
CONTROL
LOGIC
BUSY
OUTPUT
CODE
CNVST
IN–
32,768C 16,384C 4C 2C C C
LSB
MSB
AGND
AGND
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7621 is a very fast, low power, single-supply, precise,
16-bit analog-to-digital converter (ADC) using successive
approximation architecture. The AD7621 features different
modes to optimize performances according to the applications.
In warp mode, the AD7621 is capable of converting 3,000,000
samples per second (3 MSPS).
The AD7621 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7621 can be operated from a single 2.5 V supply and
be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic. It
is housed in 48-lead LQFP or tiny LFCSP packages that
combine space savings with flexibility, allowing the AD7621
to be configured as either a serial or parallel interface. The
AD7621 is pin-to-pin-compatible with, and a speed upgrade
of, the AD7677.
CONVERTER OPERATION
The AD7621 is a successive approximation analog-to-digital
converter (ADC) based on a charge redistribution DAC.
Figure 21
shows the simplified schematic of the ADC. The capacitive
DAC consists of two identical arrays of 16 binary weighted
capacitors which are connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN− inputs. A conversion
phase is initiated once the acquisition phase is complete and the
CNVST
input goes low. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the
REFGND input. Therefore, the differential voltage between the
inputs (IN+ and IN−) captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between REFGND and REF, the
comparator input varies by binary weighted voltage steps
(V
REF
/2, V
REF
/4 through V
REF
/65536). The control logic toggles
these switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition. After the
completion of this process, the control logic generates the ADC
output code and brings BUSY output low.
MODES OF OPERATION
The AD7621 features four modes of operation: wideband warp,
warp, normal, and impulse. Each of these modes is more
suitable to specific applications.
Wideband warp (WARP = high, IMPULSE = high) and warp
(WARP = high, IMPULSE = low) modes allow the fastest
conversion rate up to 3 MSPS. However, in these modes, the full
specified accuracy is guaranteed only when the time between
conversions does not exceed 1 ms. If the time between two
consecutive conversions is longer than 1 ms (after power up),
the first conversion result should be ignored. These modes
make the AD7621 ideal for applications where both high
accuracy and fast sample rate are required. Wideband warp
mode offers slightly improved linearity and THD over warp
mode.
Normal mode (WARP = low, IMPULSE = low) is the fastest
mode (2 MSPS) without any limitation on time between
conversions. This mode makes the AD7621 ideal for
asynchronous applications such as data acquisition systems,
where both high accuracy and fast sample rate are required.
Impulse mode (WARP = low, IMPULSE = high), the lowest
power dissipation mode, allows power saving between
conversions. The maximum throughput in this mode is
1.25 MSPS. In this mode, the ADC powers down circuits after
conversion making the AD7621 ideal for battery-powered
applications.
