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AD7621ACPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
AD7621
Rev. 0 | Page 3 of 32
SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
REF
= 2.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range
V
IN
+ − V
IN
−
−V
REF
V
REF
V
Operating Input Voltage V
IN
+
,
V
IN
− to AGND −0.1 AVDD
1
V
Analog Input CMRR f
IN
= 100 kHz 55 dB
Input Current 3 MSPS throughput 25 μA
Input Impedance
2
THROUGHPUT SPEED
Complete Cycle Wideband warp, warp modes 333 ns
Throughput Rate Wideband warp, warp modes 0.001 3 MSPS
Time Between Conversions Wideband warp, warp modes 1 ms
Complete Cycle Normal mode 500 ns
Throughput Rate Normal mode 0 2 MSPS
Complete Cycle Impulse mode 800 ns
Throughput Rate Impulse mode 0 1.25 MSPS
DC ACCURACY All modes
Integral Linearity Error
3
V
REF
= 2.048 V, PDREF = high −2 ±1 +2 LSB
4
No Missing Codes V
REF
= 2.048 V, PDREF = high 16 Bits
Differential Linearity Error V
REF
= 2.048 V, PDREF = high −1 +2 LSB
Transition Noise V
REF
= 2.5 V 0.69 LSB
Transition Noise V
REF
= 2.048 V 0.82 LSB
Zero Error, T
MIN
to T
MAX
5
−30 +30 LSB
Zero Error Temperature Drift ±1 ppm/°C
Gain Error, T
MIN
to T
MAX
5
−0.38 +0.38 % of FSR
Gain Error Temperature Drift ±2 ppm/°C
Power Supply Sensitivity AVDD = 2.5 V ± 5% ±3 LSB
AC ACCURACY
Dynamic Range f
IN
= 20 kHz, V
REF
= 2.5 V 90.5 dB
6
Signal-to-Noise f
IN
= 20 kHz, V
REF
= 2.5 V 88 90 dB
f
IN
= 20 kHz, V
REF
= 2.048 V 86 88 dB
f
IN
= 100 kHz, V
REF
= 2.5 V 89.2 dB
Spurious-Free Dynamic Range f
IN
= 20 kHz 103 dB
f
IN
= 100 kHz 101 dB
Total Harmonic Distortion f
IN
= 20 kHz –102 dB
f
IN
= 100 kHz −100 dB
Signal-to-(Noise + Distortion) f
IN
= 20 kHz, V
REF
= 2.5 V 87.5 89.8 dB
f
IN
= 20 kHz, V
REF
= 2.048 V 87.5 dB
f
IN
= 100 kHz, V
REF
= 2.5 V 89 dB
–3 dB Input Bandwidth 50 MHz
SAMPLING DYNAMICS
Aperture Delay 1 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 50 ns
INTERNAL REFERENCE PDREF = PDBUF = low
Output Voltage REF @ 25°C 2.038 2.048 2.058 V
Temperature Drift –40°C to +85°C ±7 ppm/°C
Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V
AD7621
Rev. 0 | Page 4 of 32
Parameter Conditions Min Typ Max Unit
Turn-On Settling Time C
REF
= 10 μF 5 ms
REFBUFIN Output Voltage REFBUFIN @ 25°C 1.2 V
REFBUFIN Output Resistance 6.33 kΩ
EXTERNAL REFERENCE PDREF = PDBUF = high
Voltage Range REF 1.8 2.048 AVDD V
Current Drain 3 MSPS throughput 250 μA
REFERENCE BUFFER PDREF = high, PDBUF = low
REFBUFIN Input Voltage Range 1.05 1.2 1.30 V
TEMPERATURE PIN
Voltage Output @ 25°C 273 mV
Temperature Sensitivity 0.85 mV/°C
Output Resistance 4.7 kΩ
DIGITAL INPUTS
Logic Levels
V
IL
–0.3 +0.6 V
V
IH
1.7 5.25 V
I
IL
–1 +1 μA
I
IH
–1 +1 μA
DIGITAL OUTPUTS
Data Format
7
Pipeline Delay
8
V
OL
I
SINK
= 500 μA 0.4 V
V
OH
I
SOURCE
= –500 μA OVDD − 0.3 V
POWER SUPPLIES
Specified Performance
AVDD 2.37 2.5 2.63 V
DVDD 2.37 2.5 2.63 V
OVDD 2.30
9
3.6 V
Operating Current
10
3 MSPS throughput
AVDD
11
With internal reference 25.2 mA
DVDD 3.6 mA
OVDD 1 mA
Power Dissipation
11
With Internal Reference
10
3 MSPS throughput 70 86 mW
Without Internal Reference
10
3 MSPS throughput 65 80 mW
With Internal Reference
12
1.25 MSPS throughput 42 55 mW
Without Internal Reference
12
1.25 MSPS throughput 37 50 mW
In Power-Down Mode
13
PD = high 600 μW
TEMPERATURE RANGE
14
Specified Performance T
MIN
to T
MAX
–40 +85 °C
1
When using an external reference. With the internal reference, the input range is −0.1 V to V
REF
.
2
See the Analog Inputs section.
3
Linearity is tested using endpoints, not best fit. Tested with an external reference at 2.048 V.
4
LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV.
5
See the Voltage Reference Input section. These specifications do not include the error contribution from the external reference.
6
All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
7
Parallel or serial 16-bit.
8
Conversion results are available immediately after completed conversion.
9
See the Absolute Maximum Ratings section.
10
In warp mode. Tested in parallel reading mode.
11
With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.
12
In impulse mode. Tested in parallel reading mode.
13
With all digital inputs forced to OVDD.
14
Consult factory for extended temperature range.
AD7621
Rev. 0 | Page 5 of 32
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
REF
= 2.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 31 and Figure 32)
Convert Pulse Width t
1
15 70
1
ns
Time Between Conversions (Warp
2
Mode/Normal Mode/Impulse Mode)
3
t
2
333/500/800 ns
CNVST Low to BUSY High Delay
t
3
23 ns
BUSY High All Modes (Except Master Serial Read After Convert) t
4
283/430/560 ns
Aperture Delay t
5
1 ns
End of Conversion to BUSY Low Delay t
6
10 ns
Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t
7
283/430/560 ns
Acquisition Time (Warp Mode/Normal Mode/Impulse Mode) t
8
50/70/50 ns
RESET Pulse Width t
9
15 ns
RESET Low to BUSY High Delay
4
t
38
10 ns
BUSY High Time from RESET Low
4
t
39
600 ns
PARALLEL INTERFACE MODES (Refer to Figure 33 and Figure 35)
CNVST Low to DATA Valid Delay
t
10
283/430/560 ns
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY Low Delay t
11
2 ns
Bus Access Request to DATA Valid t
12
20 ns
Bus Relinquish Time t
13
2 15 ns
MASTER SERIAL INTERFACE MODES
5
(Refer to Figure 37 and Figure 38)
CS Low to SYNC Valid Delay
t
14
10 ns
CS Low to Internal SCLK Valid Delay
5
t
15
10 ns
CS Low to SDOUT Delay
t
16
10 ns
CNVST Low to SYNC Delay
(Warp Mode/Normal Mode/Impulse Mode) t
17
12/137/263 ns
SYNC Asserted to SCLK First Edge Delay t
18
0.5 ns
Internal SCLK Period
6
t
19
8 12 ns
Internal SCLK High
6
t
20
2 ns
Internal SCLK Low
6
t
21
3 ns
SDOUT Valid Setup Time
6
t
22
1 ns
SDOUT Valid Hold Time
6
t
23
0 ns
SCLK Last Edge to SYNC Delay
6
t
24
0 ns
CS High to SYNC HI-Z
t
25
10 ns
CS High to Internal SCLK HI-Z
t
26
10 ns
CS High to SDOUT HI-Z
t
27
10 ns
BUSY High in Master Serial Read after Convert
6
t
28
See Table 4
CNVST Low to SYNC Asserted Delay (All Modes)
t
29
275/400/500 ns
SYNC Deasserted to BUSY Low Delay t
30
13 ns
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AD7621ACPZRL

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Buy AD7621ACPZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16B 2LSB INL 3 MSPS
Lifecycle:
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