AD7621ACPZRL Datasheet AD7621ASTZ, AD7621ACPZ, AD7621ASTZRL | P19-P21

AD7621

Rev. 0 | Page 18 of 32

coming from the driver is filtered by the AD7621 analog

input circuit one-pole, low-pass filter made by R

and C

or by the external filter, if one is used. The SNR

degradation due to the amplifier is

()

⎟

⎠

⎞

⎜

⎝

⎛

−

2809

log20

NdB

LOSS

Nef

SNR

where:

–3dB

is the input bandwidth of the AD7621 (50 MHz) or

the cutoff frequency of the input filter (16 MHz), if

one is used.

N is the noise factor of the amplifier (+1 in buffer

configuration).

is the equivalent input voltage noise density of the op

amp, in nV/√Hz.

For instance, a driver with an equivalent input noise

density of 2.1 nV/√Hz, like the AD8021 with a noise gain

of +1 when configured as a buffer, degrades the SNR by

only 0.33 dB when using the RC filter in

Figure 23, and by

1 dB without.

• The driver needs to have a THD performance suitable to

that of the AD7621.

Figure 13 gives the THD vs. frequency

that the driver should exceed.

The AD8021 meets these requirements and is appropriate for

almost all applications. The AD8021 needs a 10 pF external

compensation capacitor that should have good linearity as an

NPO ceramic or mica type. Moreover, the use of a noninverting

+1 gain arrangement is recommended and helps to obtain the

best signal-to-noise ratio.

The AD8022 can also be used when a dual version is needed

and a gain of 1 is present. The AD829 is an alternative in

applications where high frequency (above 100 kHz) performance

is not required. In applications with a gain of 1, an 82 pF

compensation capacitor is required. The AD8610 is an option

when low bias current is needed in low frequency applications.

Single-to-Differential Driver

For applications using unipolar analog signals, a single-ended-

to-differential driver, as shown in

Figure 27, allows for a

differential input into the part. This configuration, when

provided an input signal of 0 to V

REF

, will produce a differential

±V

REF

with midscale at V

REF

/2. The one-pole filter using R = 10 Ω

and C = 1 nF provides a corner frequency of 16 MHz.

If the application can tolerate more noise, the AD8139

differential driver can be used.

04565-030

AD8021

ANALOG INPUT

(UNIPOLAR 0V TO 2.048V)

AD8021

IN+

IN–

AD7621

REF

10μF

10Ω

100nF

1nF

10pF

1kΩ

590Ω

Figure 27. Single-Ended-to-Differential Driver Circuit

(Internal Reference Buffer Used)

VOLTAGE REFERENCE INPUT

The AD7621 allows the choice of either a very low temperature

drift internal voltage reference or an external reference.

Unlike many ADCs with internal references, the internal

reference of the AD7621 provides excellent performance and

can be used in almost all applications.

Internal Reference

(PDBUF = Low, PDREF = Low)

To use the internal reference, the PDREF and PDBUF inputs

must be low. This produces a 1.2 V band gap output on

REFBUFIN which, amplified by the internal buffer, results in a

2.048 V reference on the REF pin.

The internal reference is temperature-compensated to 2.048 V ±

10 mV. The reference is trimmed to provide a typical drift of

7 ppm/°C. This typical drift characteristic is shown in

Figure 7.

The output resistance of the REFBUFIN is 6.33 kΩ (minimum)

when the internal reference is enabled. It is necessary to

decouple this with a ceramic capacitor greater than 100 nF.

Thus, the capacitor provides an RC filter for noise reduction.

Since the output impedance of REFBUFIN is typically 6.33 kΩ,

relative humidity (among other industrial contaminates) can

directly affect the drift characteristics of the reference. Typically,

a guard ring is used to reduce the effects of drift under such

circumstances. However, since the AD7621 has a fine lead pitch,

guarding this node is not practical. Therefore, in these

industrial and other types of applications, it is recommended to

use a conformal coating such as Dow Corning 1-2577 or

Humiseal 1B73.

External 1.2 V Reference and Internal Buffer

(PDREF = High, PBBUF = Low)

To use an external reference with the internal buffer, PDREF

should be high and PDBUF should be low. This powers down

the internal reference and allows the 1.2 V reference to be

applied to REFBUFIN.

AD7621

Rev. 0 | Page 19 of 32

External Reference (PDBUF = High, PRBUF = High)

To use an external reference directly on the REF pin, PDREF

and PDBUF should both be high.

For improved drift performance, an external reference, such as

the AD780 or ADR431, can be used. The advantages of directly

using the external voltage reference are:

• SNR and dynamic range improvement (about 1.7 dB)

resulting from the use of a reference voltage very close to

the supply (2.5 V) instead of a typical 2.048 V reference

when the internal reference is used. This is calculated by

⎟

⎠

⎞

⎜

⎝

⎛

50.2

048.2

log20SNR

• Power savings when the internal reference is powered

down (PBREF = PDBUF = high).

PDREF and PDBUF power down the internal reference and the

internal reference buffer, respectively.

Reference Decoupling

Whether using an internal or external reference, the AD7621

voltage reference input (REF) has a dynamic input impedance;

therefore, it should be driven by a low impedance source with

efficient decoupling between the REF and REFGND inputs.

This decoupling depends on the choice of the voltage reference,

but usually consists of a low ESR capacitor connected to REF

and REFGND with minimum parasitic inductance. A 10 μF

(X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum

capacitor) is appropriate when using either the internal

reference or one of these recommended reference voltages:

• The low noise, low temperature drift ADR431 and AD780

• The low power ADR291

• The low cost AD1582

The placement of the reference decoupling is also important to

the performance of the AD7621. The decoupling capacitor

should be mounted on the same side as the ADC right at the

REF pin with a thick PCB trace. The REFGND should also

connect to the reference decoupling capacitor with the shortest

distance.

For applications that use multiple AD7621 devices, it is more

effective to use the internal reference buffer in order to buffer

the reference voltage.

The voltage reference temperature coefficient (TC) directly

impacts full scale; therefore, in applications where full-scale

accuracy matters, care must be taken with the TC. For instance,

a ±15 ppm/°C TC of the reference changes full-scale by ±1 LSB/°C.

Temperature Sensor

The TEMP pin measures the temperature of the AD7621. To

improve the calibration accuracy over the temperature range,

the output of the TEMP pin is applied to one of the inputs of the

analog switch (such as, ADG779), and the ADC itself is used to

measure its own temperature. This configuration is shown in

Figure 28.

04565-031

ADG779

AD8021

ANALOG INPUT

(UNIPOLAR)

AD7621

IN+

TEMPERATURE

SENSOR

TEMP

Figure 28. Use of the Temperature Sensor

POWER SUPPLY

The AD7621 uses three sets of power supply pins: an analog

2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a

digital input/output interface supply OVDD. The OVDD supply

allows direct interface with any logic working between 2.3 V

and 5.25 V. To reduce the number of supplies needed, the digital

core (DVDD) can be supplied through a simple RC filter from

the analog supply as shown in

Figure 23.

Power Sequencing

The AD7621 is independent of power supply sequencing once

OVDD does not exceed DVDD by more than 0.3 V until

DVDD = 2.3 V during any time; for instance, at power-up or

power-down (see the

Absolute Maximum Ratings section).

Additionally, it is very insensitive to power supply variations

over a wide frequency range as shown in

Figure 29.

04565-098

FREQUENCY (kHz)

PSRR (dB)

1 10 100 1k 10k

EXT REF

INT REF

Figure 29. PSRR vs. Frequency

AD7621

Rev. 0 | Page 20 of 32

Power-Up

At power-up, or returning to operational mode from the power-

down mode (PD = high), the AD7621 engages an initialization

process. During this time, the first 128 conversions should be

ignored or the RESET input could be pulsed to engage a faster

initialization process. Refer to the

Digital Interface section for

RESET and timing details.

A simple power-on reset circuit, as shown in

Figure 23, can be

used to minimize the digital interface. As OVDD powers up, the

capacitor is shorted and brings RESET high; it is then charged

returning RESET to low. However, this circuit only works when

powering up the AD7621 because the power down mode (PD =

high) does not power down any of the supplies. As a result,

RESET is low.

POWER DISSIPATION VS. THROUGHPUT

In impulse mode, the AD7621 automatically reduces its power

consumption at the end of each conversion phase. During the

acquisition phase, the operating currents are very low which

allows a significant power saving when the conversion rate is

reduced (see

Figure 30). This feature makes the AD7621 ideal

for very low power, battery-operated applications.

It should be noted that the digital interface remains active even

during the acquisition phase. To reduce the operating digital

supply currents even further, drive the digital inputs close to the

power rails (that is, OVDD and OGND).

04565-032

SAMPLING RATE (SPS)

POWER DISSIPATION (μW)

100

100k

10k

100 1k 10k 100k 1M 10M

WARP MODE POWER

IMPULSE MODE POWER

PDREF = PDBUF = HIGH

Figure 30. Power Dissipation vs. Sample Rate

CONVERSION CONTROL

The AD7621 is controlled by the

CNVST

input. A falling edge

CNVST

is all that is necessary to initiate a conversion.

Detailed timing diagrams of the conversion process are shown

Figure 31. Once initiated, it cannot be restarted or aborted,

even by the power-down input, PD, until the conversion is

complete. The

CNVST

signal operates independently of

and

signals.

04565-034

BUSY

MODE

CONVERT ACQUIREACQUIRE CONVERT

CNVST

Figure 31. Basic Conversion Timing

For optimal performance, the rising edge of

CNVST

should not

occur after the maximum

CNVST

low time, t

, or until the end

of conversion.

Although

CNVST

is a digital signal, it should be designed with

special care with fast, clean edges, and levels with minimum

overshoot, undershoot, or ringing.

The

CNVST

trace should be shielded with ground and a low

value (such as 50 Ω) serial resistor termination should be added

close to the output of the component that drives this line. Also,

a 60 pF capacitor is recommended to further reduce the effects

of overshoot and undershoot as shown in

Figure 23.

For applications where SNR is critical, the

CNVST

signal should

have very low jitter. This can be achieved by using a dedicated

oscillator for

CNVST

generation, or by clocking

CNVST

with a

high frequency, low jitter clock, as shown in

Figure 23.

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AD7621ACPZRL

Mfr. #:

Buy AD7621ACPZRL

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 16B 2LSB INL 3 MSPS

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AD7621ACPZRL

AD7621ACPZRL

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