10©2015 Integrated Device Technology, Inc December 14, 2015
8312I Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
Additive Phase Jitter, 3.3V @ 100MHz
12kHz to 20MHz = 0.037ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
11©2015 Integrated Device Technology, Inc December 14, 2015
8312I Datasheet
Parameter Measurement Information
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
1.8V Core/1.8V LVCMOS Output Load AC Test Circuit
3.3V Core/1.8V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
2.5V Core/1.8V LVCMOS Output Load AC Test Circuit
V
DD,
1.65V±5%
-1.65V±5%
V
DDO
V
DDO
V
DD,
0.9V±0.1V
-0.9V±0.1V
SCOPE
Qx
LVCMOS
V
DDO
2
GND
V
DDO
V
DD
0.9V±0.1V
2.4V±0.9V
-0.9V±0.1V
V
DD,
1.25V±5%
-1.25V±5%
V
DDO
SCOPE
Qx
LVCMOS
V
DDO
2
GND
V
DD
V
DDO
1.25V±5%
-1.25V±5%
2.05V±5%
SCOPE
Qx
LVCMOS
V
DDO
2
GND
V
DDO
V
DD
1.6V±5%
0.9V±0.1V
-0.9V±0.1V
12©2015 Integrated Device Technology, Inc December 14, 2015
8312I Datasheet
Parameter Measurement Information, continued
Output Skew
Propagation Delay
Output Rise/Fall Time
Part-to-Part Skew
Output Duty Cycle/Pulse Width/Period
Qx
Qy
tp
LH
tp
HL
V
DDO
2
V
DD
2
V
DDO
2
V
DD
2
CLK
Q0:Q11
20%
80%
80%
20%
t
R
t
F
Q0:Q11
t
sk(pp)
V
DDO
2
V
DDO
2
Part 1
Part 2
Qx
Qy
t
PW
t
PERIOD
V
DDO
2
V
DDO
2
V
DDO
2
t
PW
t
PERIOD
odc =
Q0:Q11

8312AYILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Low Skew,1:12 LVCMOS Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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