7©2015 Integrated Device Technology, Inc December 14, 2015
8312I Datasheet
AC Electrical Characteristics
Table 5A. AC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High; NOTE 1 ƒ 250MHz 1.2 2.0 2.7 ns
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.037 ps
tsk(o) Output Skew; NOTE 2, 5 150 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 850 ps
t
R
/ t
F
Output Rise/Fall Time; NOTE 5 20% to 80% 175 800 ps
odc Output Duty Cycle ƒ 150MHz 45 55 %
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High; NOTE 1 ƒ 250MHz 1.25 2.4 3.5 ns
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.022 ps
tsk(o) Output Skew; NOTE 2, 5 155 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 1.1 ns
t
R
/ t
F
Output Rise/Fall Time; NOTE 5 20% to 80% 200 800 ps
odc Output Duty Cycle ƒ 150MHz 45 55 %
8©2015 Integrated Device Technology, Inc December 14, 2015
8312I Datasheet
Table 5C. AC Characteristics, V
DD
= V
DDO
= 1.8V ± 0.2V, T
A
= -40°C to 85°C
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5D. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 200 MHz
tp
LH
Propagation Delay, Low to High; NOTE 1 ƒ 200MHz 1.6 3.3 4.9 ns
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.172 ps
tsk(o) Output Skew; NOTE 2, 5 160 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 2.4 ns
t
R
/ t
F
Output Rise/Fall Time; NOTE 5 20% to 80% 175 875 ps
odc Output Duty Cycle ƒ 100MHz 45 55 %
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High; NOTE 1 ƒ 250MHz 1.5 2.1 2.8 ns
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.045 ps
tsk(o) Output Skew; NOTE 2, 5 150 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 1ns
t
R
/ t
F
Output Rise/Fall Time; NOTE 5 20% to 80% 200 800 ps
odc Output Duty Cycle ƒ 150MHz 45 55 %
9©2015 Integrated Device Technology, Inc December 14, 2015
8312I Datasheet
Table 5E. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= -40°C to 85°C
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5F. AC Characteristics, V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= -40°C to 85°C
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 200 MHz
tp
LH
Propagation Delay, Low to High; NOTE 1 ƒ 200MHz 1.5 2.5 3.5 ns
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.136 ps
tsk(o) Output Skew; NOTE 2, 5 150 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 1.4 ns
t
R
/ t
F
Output Rise/Fall Time; NOTE 5 20% to 80% 200 800 ps
odc Output Duty Cycle ƒ 100MHz 45 55 %
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 200 MHz
tp
LH
Propagation Delay, Low to High; NOTE 1 ƒ 200MHz 1.4 2.7 3.9 ns
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.114 ps
tsk(o) Output Skew; NOTE 2, 5 160 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 1.6 ns
t
R
/ t
F
Output Rise/Fall Time; NOTE 5 20% to 80% 200 800 ps
odc Output Duty Cycle ƒ 100MHz 45 55 %

8312AYILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Low Skew,1:12 LVCMOS Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet