[AK4104]
MS0642-E-01 2010/09
- 10 -
OPERATION OVERVIEW
Reset and Initialization
The AK4104 should be reset once by bringing PDN = “L” upon power-up. It takes 8 bit clock cycles for the AK4104 to
initialize after PDN pin goes “H”.
MCLK and LRCK Relationship
For correct synchronization, MCLK and LRCK should be derived from the same clock signal either directly (as through a
frequency divider) or indirectly (for example, as through a DSP). The phase relationship between MCLK and LRCK
should be kept after power-up. The MCLK frequencies shown in
Table 1 are supported. The internal clock frequency is
set depending on the external MCLK frequency automatically.
MCLK Fs
128fs 16k-192kHz
192fs 16k-192kHz
256fs 8k-128kHz
384fs 8k-96kHz
512fs 8k-48kHz
768fs 8k-48kHz
1024fs 8k-32kHz
1536fs 8k-24kHz
Table 1. MCLK Frequency
[AK4104]
MS0642-E-01 2010/09
- 11 -
Audio Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 bits as shown in
Table 2 can select four
serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of
BICK. Mode 3 can be used for 16bit I
2
S Compatible format by zeroing the unused LSBs at BICK 48fs or BICK = 32fs.
Mode DIF1 DIF0 SDTI Format BICK Figure
0 0 0 16bit, LSB justified
32fs
Figure 10
1 0 1 24bit, LSB justified
48fs
Figure 11
2 1 0 24bit, MSB justified
48fs
Figure 12
3 1 1 16/24bit, I
2
S Compatible
48fs or 32fs
Figure 13
Table 2. Audio Interface Format
LRCK
BICK(32fs)
0 1102 3 9 1112131415 0 123 10109 1112131415
SDTI(i)
Don't Care 1 0 15 14 13 21015 14 13 12 12Don't Care
SDTI-15:MSB, 0:LSB
SDTI(i)
15 14 13 7654321015 14 13 1576543210
BICK(64fs)
0 1182 3 19 20 31 0 1 2 3 1018 19 20 3117 17
Lch Data Rch Data
Figure 10. Mode 0 Timing
LRCK
BICK(64fs)
0 1 22431012 10312489 89
SDTI(i)
Don't Care 0 8 10
23:MSB, 0:LSB
Lch Data Rch Data
23 8 Don't Care 231
Figure 11. Mode 1 Timing
LRCK
BICK(64fs)
0 1 220212431012 102220 21 312422 23 23
SDTI(i)
Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 231234
Figure 12. Mode 2 Timing
[AK4104]
MS0642-E-01 2010/09
- 12 -
LRCK
BICK(64fs)
0 1 22521 24 0 12 1022 2521 2422 23 233
SDTI(i)
Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 1234
Figure 13. Mode 3 Timing
DIT input select
The AK4104 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”). In 3-wire μP I/F
mode, the AK4104 can select the input data of DIT from SDTI1 or SDTI2 data.
MODE SEL1 SEL0 μP I/F DIT input
0 x x 4-wire SDTI1
1 0 0 3-wire SDTI1
1 0 1 3-wire SDTI2
1 1 0 3-wire SDTI2:DIT Bypass
1 1 1 Reserved
(x: Don’t care)
Table 3. DIT Input

AK4104ET

Mfr. #:
Manufacturer:
Description:
IC TX DGTL AUD 192KHZ 16TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet