[AK4104]
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Data Transmission Format
The Data transmitted on the TX outputs is formatted in blocks as shown in Figure 14. Each block consists of 192 frames.
A frame of data contains two sub-frames. A sub-frame consists of 32 bits of information. Each received data bit is coded
using a bi-phase mark encoding as a two binary state symbol. The preambles violate bi-phase encoding so they may be
differentiated from data. In bi-phase encoding, the first state of input symbol is always the inverse of the last state of the
previous data symbol. For a logic 0, the second state of the symbol is the same as the first state. For a logic 1, the second
state is opposite of the first.
Figure 15 illustrates a sample stream of 8 data bits encoded in 16 symbol states.
Frame 191 Frame 0 Frame 1
Sub-frame Sub-frame
M
Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2
Figure 14. Block format
0 1 1 0 0 0 1 0
Figure 15. A biphase-encoded bit stream
The sub-frame is defined in
Figure 16 below. Bits 0-3 of the sub-frame represent a preamble for synchronization. There
are three preambles. The block preamble, B, is contained in the first sub-frame of Frame 0. The channel 1 preamble, M, is
contained in the first sub-frame of all other frames. The channel 2 preamble, W, is contained in all of the second
sub-frames.
Table 4 below defines the symbol encoding for each of the preambles. Bits 4-27 of the sub-frame contain the 24 bit audio
sample in 2’s complement format with bit 27 as the most significant bit. For 16 bit mode, Bits 4-11 are all 0. Bit 28 is the
validity flag. It is “H” if the audio sample is unreliable. Bit 29 is a user data bit. Frame 0 contains the first bit of a 192 bit
user data word. Frame 191 contains the last bit of the user data word. Bit 30 is a channel status bit. Again frame 0 contains
the first bit of the 192 bit word with the last bit in frame 191. Bit 31 is an even parity bit for bits 4-31 of the sub-frame.
Sync P
C
UV
L M
S Audio sample S
B B
0 3 4 27 28 29 30 31
Figure 16. Sub-frame format
The block of data contains consecutive frames transmitted at a state-bit rate of 64 times the sample frequency, fs. For
stereophonic audio, the left or A channel data is in channel 1 while the right or B data is in channel 2. For monophonic
audio, channel 1 contains the audio data.
Preamble Preceding state = 0 Preceding state = 1
B 11101000 00010111
M 11100010 00011101
W 11100100 00011011
Table 4. Sub-frame preamble encoding
Channel Status bit
In the consumer mode (bit0 = “0”), bits20-23(audio channel) must be controlled by the CT20 bit. When the CT20 bit is
“1”, the AK4104 corresponds to “stereo mode”, bits20-23 are set to “1000”(left channel) in sub-frame 1, and is set to
“0100”(right channel) in sub-frame 2. When the CT20 bit is “0”, bits20-23 is set to “0000” in both sub-frame 1 and
sub-frame 2.
[AK4104]
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μP Control Interface
The AK4104 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”).
1.4-wire Serial mode (MODE bit = “0”, default)
The internal registers may be either written or read by the 4-wire μP interface pins: CSN, CCLK, CDTI and CDTO. The
data on this interface consists of Chip address (2bits, C1/0; fixed to “11”), Read/Write (1bit), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low
transition of CSN. CSN should be set to “H” once after the 16th CCLK.
For read operations, the CDTO output goes high
impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the
registers to their default values.
CDTI
CCLK
CSN
C1
0 1 2 34567
8 9 10 11 12 13 14 15
D4D5D6D7A1A2A3A4R/WC0 A0 D0 D1 D2 D3
CDTO
Hi-Z
WRITE
CDTI
C1 D4D5D6D7A1A2A3A4R/WC0 A 0 D0 D1 D2 D3
CDTO
Hi-Z
READ
D4D5D6D7 D0 D1 D2 D3
Hi-Z
C1-C0: Chip Address: (Fixed to “11”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 17. 4-wire μP I/F Timing
*When the AK4104 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
[AK4104]
MS0642-E-01 2010/09
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2.3-wire μP I/F mode (MODE bit = “1”)
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists
of Chip Address (2bits, C1/0; fixed to “11”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first,
5bits) and Control Data (MSB first, 8bits). The AK4104 latches the data on the rising edge of CCLK, so data should
clocked in on the falling edge. The writing of data becomes valid by 16th CCLK after a high to low transition of CSN.
CSN should be set to “H” once after the 16th CCLK. The clock speed of CCLK is 5MHz (max).
PDN pin = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers
are not initialized.
CDTI
CCLK
CSN
C1
0 1234567
8 9 10 11 12 13 14 15
D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3
C1-C0: Chip Address (Fixed to “11”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 18. 3-wire μP I/F Timing
*The AK4104 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4104 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.

AK4104ET

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Description:
IC TX DGTL AUD 192KHZ 16TSSOP
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