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LE25S40MB-AH

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LE25S40MB
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10
4. Write Disable
The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 8 Write
Disable" shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is
initiated by inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write
enable command (06h).
Figure 7 Write Enable Figure 8 Write Disable
5. Power-down
The power-down command sets all the commands, with the exception of the silicon ID read command and the
command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 9 Power-down"
shows the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by
inputting (B9h). However, a power-down command issued during an internal write operation will be ignored. The
power-down state is exited using the power-down exit command (power-down is exited also when one bus cycle or
more of the silicon ID read command (ABh) has been input). "Figure 10 Exiting from Power-down" shows the
timing waveforms of the power-down exit command.
Figure 9 Power-down Figure 10 Exiting from Power-down
SCK
SI
High Impedance
SO
CS
06h
0 1 2 3
4 5 6 7
Mode3
Mode0
8CLK
SCK
SI
High Impedance
SO
CS
04h
0 1 2 3
4 5 6 7
Mode3
Mode0
8CLK
MSB
MSB
SCK
SI
High Impedance
SO
CS
B9h
0 1 2 3
4 5 6 7
Mode3
Mode0
8CLK
SCK
SI
High Impedance
SO
CS
A
Bh
0 1 2 3
4 5 6 7
Mode3
Mode0
8CLK
t
PRB
t
DP
Power down
mode
Power down
mode
MSB
MSB
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11
6. Small Sector Erase
Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of
4K bytes. "Figure 11 Small Sector Erase" shows the timing waveforms, and Figure 20 shows a small sector erase
flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by
inputting the 24-bit addresses following (20h) or (D7h). Addresses A18 to A12 are valid, and Addresses A23 to A19
are "don't care". After the command has been input, the internal erase operation starts from the rising CS
edge, and it
ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register
RDY
.
Figure 11 Small Sector Erase
7. Sector Erase
Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64K bytes.
"Figure 12 Sector Erase" shows the timing waveforms, and Figure 20 shows a sector erase flowchart. The sector
erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses
following (D8h). Addresses A18 to A16 are valid, and Addresses A23 to A19 are "don't care". After the command
has been input, the internal erase operation starts from the rising CS
edge, and it ends automatically by the control
exercised by the internal timer. Erase end can also be detected using status register RDY
.
Figure 12 Sector Erase
Self-timed
Erase Cycle
SCK
SI
High Impedance
SO
CS
t
SSE
Add.
20h / D7h
Add. Add.
15
0 1 2 3
4 5 6 7 8 2316 24 31
Mode3
Mode0
8CLK
MSB
SCK
SI
High Impedance
SO
CS
t
SE
Self-timed
Erase Cycle
Add. D8h Add. Add.
15
0 1 2 3
4 5 6 7 8 2316 24 31
Mode3
Mode0
8CLK
MSB
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12
8. Chip Erase
Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 13 Chip Erase" shows the
timing waveforms, and Figure 20 shows a chip erase flowchart. The chip erase command consists only of the first
bus cycle, and it is initiated by inputting (60h) or (C7h). After the command has been input, the internal erase
operation starts from the rising CS
edge, and it ends automatically by the control exercised by the internal timer.
Erase end can also be detected using status register RDY
.
Figure 13 Chip Erase
9. Page Program
Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page
(page addresses: A18 to A8). Before initiating page program, the data on the page concerned must be erased using
small sector erase, sector erase, or chip erase. "Figure 14 Page Program" shows the page program timing waveforms,
and Figure 21 shows a page program flowchart. After the falling CS
, edge, the command (02H) is input followed by
the 24-bit addresses. Addresses A18 to A0 are valid. The program data is then loaded at each rising clock edge until
the rising CS
edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes,
the 256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program
operation is not performed at the rising CS
edge occurring at any other timing.
Figure 14 Page Program
SCK
SI
High Impedance
SO
CS
t
CHE
Self-timed
Erase Cycle
60h / C7h
0 1 2 3 4 5 6 7
Mode3
Mode0
8CLK
MSB
t
PP
Self-timed
Program Cycle
SCK
SI
High Impedance
SO
CS
PD
A
dd.
A
dd. 02h
A
dd. PD
15
0 1 2 3
4 5 6 7 8 2316 24 31 32 39 40 47
Mode3
Mode0
8CLK
PD
2079
MSB
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LE25S40MB-AH

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Manufacturer:
ON Semiconductor
Description:
NOR Flash FLASH MEMORY
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