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LE25S40MB-AH

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LE25S40MB
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13
10. Silicon ID Read
ID read is an operation that reads the manufacturer code and device ID information. The silicon ID read command is
not accepted during writing. There are two methods of reading the silicon ID, each of which is assigned a device ID.
In the first method, the read command sequence consists only of the first bus cycle in which (9Fh) is input. In the
subsequent bus cycles, the manufacturer code 62h which is assigned by JEDEC, 2-byte device ID code (memory
type, memory capacity), and reserved code are output sequentially. The 4-byte code is output repeatedly as long as
clock inputs are present,
"Table 7-1 JEDEC ID code " lists the silicon ID codes and "Figure 15-a JEDEC ID read"
shows the JEDEC ID read timing waveforms.
The second method involves inputting the ID read command. This command consists of the first through fourth bus
cycles, and the one bite silicon ID can be read when 24 dummy bits are input after (ABh). "Table 7-2 ID code " lists
the silicon ID codes and "Figure 15-b ID read" shows the ID read timing waveforms.
If the SCK input persists after a device code is read, that device code continues to be output. The data output is
transmitted starting at the falling edge of the clock for bit 0 in the fourth bus cycle and the silicon ID read sequence
is finished by setting CS
high.
Table 7-1 JEDEC ID code Table 7-2 ID code
Output code
Output Code
Manufacturer code
62h
1 byte device ID
3E
(LE25S40MB)
2 byte device ID
Memory type
16h
Memory capacity code
13h(4M Bit)
Device code 1
00h
Figure 15-a JEDEC ID Read
Figure 15-b ID Read
CS
High Impedance
13h 16h 62h
SCK
SO
SI
9Fh
15
MSB MSB MSB
0 1 2 3
4 5 6 7 8 2316 24 31 39
8CL
Mode0
Mode3
32
00h
MSB
62h
MSB
CS
High Impedance
3Eh 3Eh
SCK
SO
SI
A
Bh X X
15
MSB MSB
0 1 2 3
4 5 6 7 8 2316 24 31 39
8CL
Mode0
Mode3
32
X
LE25S40MB
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14
11. Hold Function
Using the HOLD
pin, the hold function suspends serial communication (it places it in the hold status). "Figure16
HOLD
" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the
logic level of SCK is low, and it exits from the hold status at the rising HOLD
edge. When the logic level of SCK is
high, HOLD
must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is
exited and serial communication is reset at the rising CS
edge. In the hold status, the SO output is in the high-
impedance state, and SI and SCK are "don't care".
Figure 16 HOLD
12. Power-on
In order to protect against unintentional writing, CS
must be within at V
DD
-0.3 to V
DD
+0.3 on power-on. After
power-on, the supply voltage has stabilized at VDD min. or higher, waits for t
PU
before inputting the command to
start a device operation. The device is in the standby state and not in the power-down state after power is turned on.
To put the device into the power-down state, it is necessary to enter a power-down command.
Figure 17 Power-on Timing
CS
HOLD
SCK
SO
ctive
HOLD
ctive
t
HH
t
HS
t
HLZ
t
HHZ
High Impedance
t
HH
t
HS
V
DD
(Max)
V
DD
(Min)
V
DD
0V
t
PU
CS
= V
DD
level
Full Access Allowed
LE25S40MB
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15
13. Hardware Data Protection
LE25S40MB incorporates a power-on reset function. The following conditions must be met in order to ensure that
the power reset circuit will operate stably.
No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.
Figure 18 Power-down Timing
Power-on timing
Parameter Symbol
spec
unit
min max
power-on to operation time t
PU
100 µs
power-down time t
PD
10 ms
power-down voltage t
BOT
0.2 V
14. Software Data Protection
The LE25S40MB eliminates the possibility of unintentional operations by not recognizing commands under the
following conditions.
When a write command is input and the rising CS
edge timing is not in a bus cycle (8 CLK units of SCK)
When the page program data is not in 1-byte increments
When the status register write command is input for 2 bus cycles or more
15. Decoupling Capacitor
A 0.1 F ceramic capacitor must be provided to each device and connected between V
DD
and V
SS
in order to
ensure that the device will operate stably.
V
DD
(Max)
V
DD
(Min)
V
DD
0V
vBOT
t
PD
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LE25S40MB-AH

Mfr. #:
Buy LE25S40MB-AH
Manufacturer:
ON Semiconductor
Description:
NOR Flash FLASH MEMORY
Lifecycle:
New from this manufacturer.
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