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LE25S40MB-AH

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LE25S40MB
www.onsemi.com
4
Device Operation
The read, erase, program and other required functions of the device are executed through the command registers.
The serial I/O corrugate is shown in Figure 3 and the command list is shown in Table 2. At the falling CS
edge the
device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are normalized in 8 bit
units and taken into the device interior in synchronization with the rising edge of SCK, which causes the device to
execute operation according to the command that is input.
The LE25S40MB supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS
edge, SPI mode 0 is
automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of
SCK is high.
Figure 3 I/O waveforms
Table 2 Command Settings
Command 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle Nth bus cycle
Read
03h A23-A16 A15-A8 A7-A0 RD *1 RD *1 RD *1
0Bh A23-A16 A15-A8 A7-A0 X RD *1 RD *1
Small sector erase
20h / D7h A23-A16 A15-A8 A7-A0
Sector erase
D8h A23-A16 A15-A8 A7-A0
Chip erase
60h / C7h
Page program
02h A23-A16 A15-A8 A7-A0 PD *2 PD *2 PD *2
Write enable
06h
Write disable
04h
Power down
B9h
Status register read
05h
Status register write
01h DATA
JEDEC ID read
9Fh
ID read
ABh X X X
power down
B9h
Exit power down mode
ABh
Explanatory notes for Table 2
"X" signifies "don't care" (that is to say, any value may be input).
The "h" following each code indicates that the number given is in hexadecimal notation.
Addresses A23 to A19 for all commands are "Don't care".
*1: "RD" stands for read data. *2: "PD" stands for page program data.
CS
SCK
SO
SI
High Impedance
DATA
DATA
1st bus 2nd bus
8CLK
Mode0
Mode3
Nth bus
MSB
(Bit7)
LSB
(Bit0)
LE25S40MB
www.onsemi.com
5
Table 3 Command Settings
4M bit
sector(64KB) small sector address space(A23 to A0)
7
127 07F000h 07FFFFh
to
112 070000h 070FFFh
6
111 06F000h 06FFFFh
to
96 060000h 060FFFh
5
95 05F000h 05FFFFh
to
80 050000h 050FFFh
4
79 04F000h 04FFFFh
to
64 040000h 040FFFh
3
63 03F000h 03FFFFh
to
48 030000h 030FFFh
2
47 02F000h 02FFFFh
to
32 020000h 020FFFh
1
31 01F000h 01FFFFh
to
16 010000h 010FFFh
0
15 00F000h 00FFFFh
to
2 002000h 002FFFh
1 001000h 001FFFh
0 000000h 000FFFh
LE25S40MB
www.onsemi.com
6
Description of Commands and Their Operations
A detailed description of the functions and operations corresponding to each command is presented below.
1. Standard SPI read
There are two read commands, the standard SPI read command and High-speed read command.
1-1. Read command
Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses
following (03h). The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference.
"Figure 4-a Read" shows the timing waveforms.
Figure 4-a Read
1-2. High-speed Read command
Consisting of the first through fifth bus cycles, the High-speed read command inputs the 24-bit addresses and 8
dummy bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a
reference. "Figure 4-b High-speed Read" shows the timing waveforms.
Figure 4-b High-speed Read
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the
highest address (7FFFFh), the internal address returns to the lowest address (00000h), and data output is continued.
By setting the logic level of CS
to high, the device is deselected, and the read cycle ends. While the device is
deselected, the output pin SO is in a high-impedance state.
N+2 N+1 N
CS
High Impedance
DATA DATA DATA
SCK
SO
SI
03h
A
dd.
A
dd.
A
dd.
15
MSB MSB MSB
0 1 2 3 4 5 6 7 8 23 16 24 31 39 47
8CLK
Mode0
Mode3
32 40
N+2 N+1 N
CS
High Impedance
DATA DATA DATA
SCK
SO
SI
0Bh
A
dd.
A
dd.
A
dd. X
15
MSB MSB MSB
0 1 2 3 4 5 6 7 8 2316 24 31 32 39 40 47 48 55
Mode3
Mode0
8CLK
MSB
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

LE25S40MB-AH

Mfr. #:
Buy LE25S40MB-AH
Manufacturer:
ON Semiconductor
Description:
NOR Flash FLASH MEMORY
Lifecycle:
New from this manufacturer.
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